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Verilog question

J

Thread Starter

Joe24

Joined May 18, 2007
52
Hello all,

I have the following code:

reg [3:0]cntr;


always@(posedge clk or posedge rst)
if(rst)
cntr_stop<=1'b0;
else
if(&cntr)
cntr_stop<=1'b1;


Where I am confused about is the if(&cntr) part.... What does &cntr represent???

Many thanks in advance
 
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