Verilog Instantiateion

Discussion in 'The Projects Forum' started by thisonedude, Jul 18, 2014.

  1. thisonedude

    Thread Starter Member

    Apr 20, 2014
    i need help Instantiating an edge triggered D Flip FLip in a verilog code twice. I have to implement the following diagram: ( see figure) have the following codes:
    // A gated RS latch
    module lab4_GDL(Clk, D, Q);
    input Clk, D;
    output Q;

    wire R_g, S_g, Qa, Qb /* synthesis keep */;
    assign R = ~D;
    assign R_g = ~(R & ~Clk);
    assign S_g = ~(D & ~Clk);
    assign Qb = ~(R_g & Qa);
    assign Qa = ~(S_g & Qb);

    assign Q = Qa;


    //DE2 board implementation

    module D_F_F(SW, LEDR, LEDR1, LEDR2);
    parameter n = 32;
    input [1:0] SW;
    output[n-1:0] LEDR;
    output[n-1:0] LEDR1;
    output[n-1:0] LEDR2;
    wire D, Clk, Q, Qbar, Qm, Qs;

    assign D = SW[0];
    assign Clk = SW[1];

    assign LEDR = Qbar;
    assign LEDR1 = Q;
    assign LEDR2 = Qm;

    lab4_GDL f1(.Q(Q), .D(D), .Clk(Clk));

    lab4_GDL f2(.Q(Qs), .D(Qm), .Clk(Clk));


    How do i instatiate it so that i can keep the output of the first block as the input of the second? help please?
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