Hi
I would consider myself a novice in verilog. So here is the code that my teacher gave us for an unsigned multiplier, but I can't seem to get an output from it. Can anyone help? I wrote a testbench to test different inputs and get nothing for the output. I am trying to instantiate this in a 5x5 signed multiplier for the project, but his code isn't working. Here's the code:
I would consider myself a novice in verilog. So here is the code that my teacher gave us for an unsigned multiplier, but I can't seem to get an output from it. Can anyone help? I wrote a testbench to test different inputs and get nothing for the output. I am trying to instantiate this in a 5x5 signed multiplier for the project, but his code isn't working. Here's the code:
Rich (BB code):
module mult4x4(clk, st, mplier, mcand, prod, done);
input clk;
input st;
input [3:0] mplier, mcand;
output [8:0] prod; //added
output done;
reg done;
reg [3:0] pstate,nstate;
reg [8:0] prod;
parameter s0=4'b0000, s1=4'b0001, s2=4'b0010, s3=4'b0011;
parameter s4=4'b0100, s5=4'b0101, s6=4'b0110, s7=4'b0111;
parameter s8=4'b1000, s9=4'b1001;
reg [8:0] ACC; //accumulator
//reg M=ACC[0]; //M is bit 0 of ACC; could use 'define
wire M;
assign M = ACC[0];
always @(posedge clk or posedge st)
if (st) pstate = s0;
else pstate = nstate;
always @(pstate) //state transition
case (pstate)
s0: if(st) nstate = s1;
s1: if (M) nstate = s2; else nstate = s3;
s2: nstate = s3;
s3: if (M) nstate = s4; else nstate = s5;
s4: nstate = s5;
s5: if (M) nstate = s6; else nstate = s7;
s6: nstate = s7;
s7: if (M) nstate = s8; else nstate = s9;
s8: nstate = s9;
s9: nstate = s0;
endcase
always @(pstate) //Output (Action)
case (pstate)
s0: begin
ACC[8:4] = 5'b00000;
ACC[3:0] = mplier;
end
s1: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
s2: ACC = {1'b0, ACC[8:1]};
s3: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
s4: ACC = {1'b0, ACC[8:1]};
s5: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
s6: ACC = {1'b0, ACC[8:1]};
s7: ACC[8:4] = {1'b0, ACC[7:4]} + {1'b0, mcand};
s8: ACC = {1'b0, ACC[8:1]};
s9: begin
done = 1'b1;
prod = ACC;
end
endcase
endmodule
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