verilog driving me crazy-parameters won't pass

Discussion in 'Embedded Systems and Microcontrollers' started by Tired guy, May 4, 2012.

  1. Tired guy

    Thread Starter New Member

    Apr 17, 2012
    So, I've battled for days with Xilinx ISE 13 and 10.1 and gave up on understanding how to use it. now i'm using Icarus 0.9.5
    so my problem is the following: no matter what I try, I keep getting x/z values when printing out carry in/out, since using an operator on x/z gives us x/z, the sum turns out x/z

    Code ( (Unknown Language)):
    1. [FONT=Courier New]module behavior_fa(b1,b2,carry_in, sum, carry_out);[/FONT]
    2. [FONT=Courier New] input b1, b2, carry_in;[/FONT]
    3. [FONT=Courier New] output carry_out, sum;[/FONT]
    4. [FONT=Courier New] reg r_c_out, r_sum;[/FONT]
    5. [FONT=Courier New] reg [3:1] tmp;[/FONT]
    6. [FONT=Courier New] initial begin[/FONT]
    7. [FONT=Courier New] tmp[3]<=b1;[/FONT]
    8. [FONT=Courier New] tmp[2]<=b2;[/FONT]
    9. [FONT=Courier New] tmp[1]<=carry_in;[/FONT]
    10. [FONT=Courier New] r_c_out=0;[/FONT]
    11. [FONT=Courier New] r_sum=0; //this will save me some blocks[/FONT]
    12. [FONT=Courier New] $display("b1=%b,b2=%b,c_in=%b",tmp[3],tmp[2],carry_in);[/FONT]
    13. [FONT=Courier New] case (tmp)[/FONT]
    14. [FONT=Courier New] 3'b001: r_sum=1;[/FONT]
    15. [FONT=Courier New] 3'b010:   r_sum=1;[/FONT]
    16. [FONT=Courier New] 3'b100:   r_sum=1;[/FONT]
    17. [FONT=Courier New] 3'b011:   r_c_out=1;[/FONT]
    18. [FONT=Courier New] 3'b110:   r_c_out=1;[/FONT]
    19. [FONT=Courier New] 3'b101:   begin[/FONT]
    20. [FONT=Courier New]          r_c_out=1;[/FONT]
    21. [FONT=Courier New]          $display("no fail");[/FONT]
    22. [FONT=Courier New]          end[/FONT]
    23. [FONT=Courier New] 3'b111:   begin[/FONT]
    24. [FONT=Courier New]          r_c_out=1;[/FONT]
    25. [FONT=Courier New]          r_sum=1;[/FONT]
    26. [FONT=Courier New]       end[/FONT]
    27. [FONT=Courier New] endcase[/FONT]
    28. [FONT=Courier New] $display("behavior fa b1=%b,b2=%b,sum=%b,carry_in=%b,carry_out=%b",b1,b2,sum,carry_in,r_c_out);[/FONT]
    30. [FONT=Courier New] end[/FONT]
    31. [FONT=Courier New] assign carry_out=r_c_out;[/FONT]
    32. [FONT=Courier New] assign sum=r_sum;[/FONT]
    33. [FONT=Courier New]endmodule[/FONT]
    44. [FONT=Courier New]module behavior_ha(b1,b2,sum,carry);[/FONT]
    45. [FONT=Courier New] input b1,b2;[/FONT]
    46. [FONT=Courier New] output sum,carry;[/FONT]
    47. [FONT=Courier New] reg sum_r,carry_r;[/FONT]
    52. [FONT=Courier New] initial begin[/FONT]
    53. [FONT=Courier New] carry_r=0; //makes the code easier for me, don't need to use begins[/FONT]
    54. [FONT=Courier New] sum_r=0; //same deal, makes shorter code, I guess it saves us some gates/checks too[/FONT]
    55. [FONT=Courier New] if (b1==0)[/FONT]
    56. [FONT=Courier New]    if (b2==1)[/FONT]
    57. [FONT=Courier New]       sum_r=1;[/FONT]
    58. [FONT=Courier New] else if (b1==1)[/FONT]
    59. [FONT=Courier New]    if (b2==0)[/FONT]
    60. [FONT=Courier New]       sum_r=1;[/FONT]
    61. [FONT=Courier New]    else if (b2==1)[/FONT]
    62. [FONT=Courier New]       carry_r=1;[/FONT]
    63. [FONT=Courier New] $display("behavior ha b1=%b,b2=%b,sum=%b,carry=%b",b1,b2,sum,carry);[/FONT]
    68. [FONT=Courier New] end[/FONT]
    69. [FONT=Courier New] assign sum=sum_r;[/FONT]
    70. [FONT=Courier New] assign carry=carry_r; //just added these 2, don't know if it'll work[/FONT]
    71. [FONT=Courier New]endmodule //i do "else if" and not just "else" in case b1 or b2 is X or Z[/FONT]
    78. [FONT=Courier New]module behavior_8_bit_adder(in1, in2, sum);[/FONT]
    79. [FONT=Courier New] input [7:0] in1;[/FONT]
    80. [FONT=Courier New] input [7:0] in2;[/FONT]
    81. [FONT=Courier New] output [7:0] sum;[/FONT]
    82. [FONT=Courier New] wire [7:1] carry;[/FONT]
    83. [FONT=Courier New] behavior_ha b1(0,0,sum[0],carry[1]);[/FONT]
    84. [FONT=Courier New] behavior_fa #15 b2(0,0,carry[1],sum[1],carry[2]);[/FONT]
    85. [FONT=Courier New] behavior_fa #30 b3(0,0,carry[2],sum[2],carry[3]);[/FONT]
    86. [FONT=Courier New] behavior_fa #45 b4(1,1,carry[3],sum[3],carry[4]);[/FONT]
    87. [FONT=Courier New] behavior_fa #60 b5(1,0,carry[4],sum[4],carry[5]);[/FONT]
    88. [FONT=Courier New] behavior_fa #75 b6(0,0,carry[5],sum[5],carry[6]);[/FONT]
    89. [FONT=Courier New] behavior_fa #90 b7(0,0,carry[6],sum[6],carry[7]);[/FONT]
    90. [FONT=Courier New] behavior_fa #105 b8(0,0,carry[7],sum[7],);[/FONT]
    92. [FONT=Courier New] initial begin[/FONT]
    93. [FONT=Courier New]    #5 $display("num1=%d, num2=%d, sum=%d (behavior)",in1,in2,sum);[/FONT]
    94. [FONT=Courier New] end[/FONT]
    95. [FONT=Courier New]endmodule[/FONT]
    I tried removing the intialization (which was ignored, at least by Xilinx ISE 10.1 - it said it ignored the initialization because the registers got a value later, in the if-s). didn't help.

    I've done the same with the dataflow model and the structual model and it works fine (didn't even have to put the delay before instances of the full adder. should I thought?)


    oh, and If someone is wondering why I wrote a half adder AND a full adder- that's the assignment
  2. guitarguy12387

    Active Member

    Apr 10, 2008
    This code will definitely not synthesize. It's a little confusing to see what's going on, but x's mean that a signal is not being driven, FYI. But that's the least of your worries at this point.

    When writing HDL, you want to have a circuit in mind before you start writing a line of code. Think about what it takes to make your adder circuit. I see you've identified that you are using a half adder and some full adders. Good. Now what type of circuit do you need to get that? How does the code you write translate into that circuit? You can build half/full adders with xors, ands, and ors. The circuit you described does not use these synthesizable constructs.

    FYI, case statment is generally intended to infer a MUX. Also, initial blocks are not synthesizable.

    Another thing you should do is think about separating your design from your testbench. Your design should generally be synthesizable and you bolt a testbench onto it to create stimulus and monitor outputs. Since the testbench will eventually pulled back off, your testbench may use non-synthesizable constructs.

    Lastly, if you plan on furthering your career in digital logic (especially for FPGAs), stick with ISE/Planahead or Quartus (IMHO). They're industry standard, the free versions are very powerful, and you will learn a lot from them.
  3. Tired guy

    Thread Starter New Member

    Apr 17, 2012
    well, the assignments says I must do the same thing for behavioral model, dataflow and structural. the way I understand it, behavioral model means blocks and if-s/cases

    as for having a circuit in mind - I did, but not for the behavioral model. it's much easier to imagine it in the other models

    I tried separating my design from my testbench. same problem - same problem (parameters didn't pass)

    and I have no intention of working as a programmer. yesterday was the first time in years I stayed up until late at night working on a program

    so forget synthesizable or not, I want this code to work, any Idea why it doesn't? I need to submit an 8-bit adder with behavioral model and that's how I understand behavioral model looks...
    Last edited: May 5, 2012
  4. Tired guy

    Thread Starter New Member

    Apr 17, 2012
    (why can't I edit my posts?)
    so I re-wrote the full adder code, turns out the assignment with the temp registers was a problem or something... i'm not sure
    with the new code, carry_out is no longer z's or x's (don't remember what it was).
    but carry_in remains z's, I suppose because the output is registers and the input should be wires...
    here's the new code:
    Code ( (Unknown Language)):
    1. module behavior_fa(b1,b2,carry_in, sum, carry_out);
    2.     input b1, b2, carry_in;
    3.     output sum,carry_out;
    4.     reg sum,carry_out;
    6. //  $display("after initial, b1=%b,b2=%b,carry=%b",b1,b2,carry_in);
    8.     initial begin
    9.     if (b1==1)
    10.         if (b2==1) begin
    11.             if (carry_in==1)
    12.                 sum=1;
    13.             else
    14.                 sum=0;
    15.             carry_out=1;
    16.         end
    17.         else
    18.             if (carry_in==1) begin
    19.                 sum=0;
    20.                 carry_out=1;
    21.             end
    22.             else begin
    23.                 sum=1;
    24.                 carry_out=0;
    25.             end
    27.     else
    28.         if (b2==1)
    29.             if (carry_in==1) begin
    30.                 sum=0;
    31.                 carry_out=1;
    32.             end
    33.             else begin
    34.                 carry_out=0;
    35.                 sum=1;
    36.             end
    37.         else begin
    38.             if (carry_in==1)
    39.                 sum=1;
    40.             else
    41.                 sum=0;
    42.             carry_out=0;
    43.         end
    44.     $display("behavior fa b1=%b,b2=%b,carry_in=%b,sum=%b,carry_out=%b",b1,b2,carry_in,sum,carry_out);
    46.     end
    47. endmodule
    I think i've seen variables declared twice (once as wire and once as reg) in the same module, but i'm not sure how =/
    Last edited: May 5, 2012
  5. Tired guy

    Thread Starter New Member

    Apr 17, 2012
    so I've changed "initial" to "always" + sensitivity list and it works... this is confusing me. anyway, the test bench still doesn't work. It calls adder, but there's an initial block there with $display and it doesn't display the text =/
  6. Tired guy

    Thread Starter New Member

    Apr 17, 2012
    Now i just feel like an idiot... made a very dumb mistake... you can erase this thread for all i care :p