verilog driving me crazy-parameters won't pass

Thread Starter

Tired guy

Joined Apr 17, 2012
11
So, I've battled for days with Xilinx ISE 13 and 10.1 and gave up on understanding how to use it. now i'm using Icarus 0.9.5
so my problem is the following: no matter what I try, I keep getting x/z values when printing out carry in/out, since using an operator on x/z gives us x/z, the sum turns out x/z

Rich (BB code):
module behavior_fa(b1,b2,carry_in, sum, carry_out);
 input b1, b2, carry_in;
 output carry_out, sum;
 reg r_c_out, r_sum;
 reg [3:1] tmp;
 initial begin
 tmp[3]<=b1;
 tmp[2]<=b2;
 tmp[1]<=carry_in;
 r_c_out=0;
 r_sum=0; //this will save me some blocks
 $display("b1=%b,b2=%b,c_in=%b",tmp[3],tmp[2],carry_in);
 case (tmp)
 3'b001: r_sum=1;
 3'b010:   r_sum=1;
 3'b100:   r_sum=1;
 3'b011:   r_c_out=1;
 3'b110:   r_c_out=1;
 3'b101:   begin
          r_c_out=1;
          $display("no fail");
          end
 3'b111:   begin
          r_c_out=1;
          r_sum=1;
       end
 endcase
 $display("behavior fa b1=%b,b2=%b,sum=%b,carry_in=%b,carry_out=%b",b1,b2,sum,carry_in,r_c_out);
 
 end
 assign carry_out=r_c_out;
 assign sum=r_sum;
endmodule
 
 
 
 
 
 
 
 
 
 
module behavior_ha(b1,b2,sum,carry);
 input b1,b2;
 output sum,carry;
 reg sum_r,carry_r;
 
 
 
 
 initial begin
 carry_r=0; //makes the code easier for me, don't need to use begins
 sum_r=0; //same deal, makes shorter code, I guess it saves us some gates/checks too
 if (b1==0)
    if (b2==1)
       sum_r=1;
 else if (b1==1)
    if (b2==0)
       sum_r=1;
    else if (b2==1)
       carry_r=1;
 $display("behavior ha b1=%b,b2=%b,sum=%b,carry=%b",b1,b2,sum,carry);
 
 
 
 
 end
 assign sum=sum_r;
 assign carry=carry_r; //just added these 2, don't know if it'll work
endmodule //i do "else if" and not just "else" in case b1 or b2 is X or Z
 
 
 
 
 
 
module behavior_8_bit_adder(in1, in2, sum);
 input [7:0] in1;
 input [7:0] in2;
 output [7:0] sum;
 wire [7:1] carry;
 behavior_ha b1(0,0,sum[0],carry[1]);
 behavior_fa #15 b2(0,0,carry[1],sum[1],carry[2]);
 behavior_fa #30 b3(0,0,carry[2],sum[2],carry[3]);
 behavior_fa #45 b4(1,1,carry[3],sum[3],carry[4]);
 behavior_fa #60 b5(1,0,carry[4],sum[4],carry[5]);
 behavior_fa #75 b6(0,0,carry[5],sum[5],carry[6]);
 behavior_fa #90 b7(0,0,carry[6],sum[6],carry[7]);
 behavior_fa #105 b8(0,0,carry[7],sum[7],);
 
 initial begin
    #5 $display("num1=%d, num2=%d, sum=%d (behavior)",in1,in2,sum);
 end
endmodule
I tried removing the intialization (which was ignored, at least by Xilinx ISE 10.1 - it said it ignored the initialization because the registers got a value later, in the if-s). didn't help.

I've done the same with the dataflow model and the structual model and it works fine (didn't even have to put the delay before instances of the full adder. should I thought?)

thanks!

oh, and If someone is wondering why I wrote a half adder AND a full adder- that's the assignment
 

guitarguy12387

Joined Apr 10, 2008
359
This code will definitely not synthesize. It's a little confusing to see what's going on, but x's mean that a signal is not being driven, FYI. But that's the least of your worries at this point.

When writing HDL, you want to have a circuit in mind before you start writing a line of code. Think about what it takes to make your adder circuit. I see you've identified that you are using a half adder and some full adders. Good. Now what type of circuit do you need to get that? How does the code you write translate into that circuit? You can build half/full adders with xors, ands, and ors. The circuit you described does not use these synthesizable constructs.

FYI, case statment is generally intended to infer a MUX. Also, initial blocks are not synthesizable.

Another thing you should do is think about separating your design from your testbench. Your design should generally be synthesizable and you bolt a testbench onto it to create stimulus and monitor outputs. Since the testbench will eventually pulled back off, your testbench may use non-synthesizable constructs.

Lastly, if you plan on furthering your career in digital logic (especially for FPGAs), stick with ISE/Planahead or Quartus (IMHO). They're industry standard, the free versions are very powerful, and you will learn a lot from them.
 

Thread Starter

Tired guy

Joined Apr 17, 2012
11
well, the assignments says I must do the same thing for behavioral model, dataflow and structural. the way I understand it, behavioral model means blocks and if-s/cases

as for having a circuit in mind - I did, but not for the behavioral model. it's much easier to imagine it in the other models

I tried separating my design from my testbench. same problem - same problem (parameters didn't pass)

and I have no intention of working as a programmer. yesterday was the first time in years I stayed up until late at night working on a program

so forget synthesizable or not, I want this code to work, any Idea why it doesn't? I need to submit an 8-bit adder with behavioral model and that's how I understand behavioral model looks...
 
Last edited:

Thread Starter

Tired guy

Joined Apr 17, 2012
11
(why can't I edit my posts?)
so I re-wrote the full adder code, turns out the assignment with the temp registers was a problem or something... i'm not sure
with the new code, carry_out is no longer z's or x's (don't remember what it was).
but carry_in remains z's, I suppose because the output is registers and the input should be wires...
here's the new code:
Rich (BB code):
module behavior_fa(b1,b2,carry_in, sum, carry_out);
	input b1, b2, carry_in;
	output sum,carry_out;
	reg sum,carry_out;

//	$display("after initial, b1=%b,b2=%b,carry=%b",b1,b2,carry_in);

	initial begin
	if (b1==1)
		if (b2==1) begin
			if (carry_in==1)
				sum=1;
			else
				sum=0;
			carry_out=1;
		end
		else
			if (carry_in==1) begin
				sum=0;
				carry_out=1;
			end
			else begin
				sum=1;
				carry_out=0;
			end
		
	else
		if (b2==1)
			if (carry_in==1) begin
				sum=0;
				carry_out=1;
			end
			else begin
				carry_out=0;
				sum=1;
			end
		else begin
			if (carry_in==1)
				sum=1;
			else
				sum=0;
			carry_out=0;
		end
	$display("behavior fa b1=%b,b2=%b,carry_in=%b,sum=%b,carry_out=%b",b1,b2,carry_in,sum,carry_out);
	
	end
endmodule
I think i've seen variables declared twice (once as wire and once as reg) in the same module, but i'm not sure how =/
 
Last edited:

Thread Starter

Tired guy

Joined Apr 17, 2012
11
so I've changed "initial" to "always" + sensitivity list and it works... this is confusing me. anyway, the test bench still doesn't work. It calls adder, but there's an initial block there with $display and it doesn't display the text =/
 
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