# Verilog compilation error when attempting to output to LED

#### Obanion

Joined Nov 26, 2009
24
EDIT: Figured it out. I assigned the LEDR[0] wire to the value of a register that I put in place of the LEDR[0]. I guess it makes sense since you cannot have a wire acting as a register.

Hi guys,

I'm trying to get this block working. I get the error:

Rich (BB code):
Error (10137): Verilog HDL Procedural Assignment error at PWM.v(34): object "LEDR" on left-hand side of assignment must have a variable data type
Here is the code causing the error:

Rich (BB code):
   always @ (posedge myclock[6])
begin
if(RST)
counter = 8'h00;
else if (counter < vc)
begin
LEDR[0] = 1'b1;
counter = counter + 1;
end
else
begin
LEDR[0] = 1'b0;
counter = counter + 1;
end
end
I have the LED declared as an output:

Rich (BB code):
output  [17:0] LEDR
Any ideas why this isn't working? I tried using "assign" in front of it, but it still doesn't seem to work. I suspect it's something simple, but my Verilog skills aren't yet developed. I'd appreciate it if someone could shed some light on this issue.

Thanks,

Obby

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Last edited: