a circuit has input node "adc_busy" ,but it depends on circuit's output "trim_code" i.e. as output trim_code changes ,after 10 cycles the input "adc_busy" goes from 1 to 0. Now, in verilog code if I am declaring adc_busy as input ,it gives error (telling that input adc_busy is wire)...Please suggest some code so that adc_busy will be input which depends on output "trim_code" ,so that I can see adc_busy waveform.