verilog code line so that I can see the waveform of an input which DEPENDS ON PUTPUT

Discussion in 'Homework Help' started by yagyasen, Jun 28, 2013.

  1. yagyasen

    Thread Starter New Member

    Jun 18, 2013
    a circuit has input node "adc_busy" ,but it depends on circuit's output "trim_code" i.e. as output trim_code changes ,after 10 cycles the input "adc_busy" goes from 1 to 0. Now, in verilog code if I am declaring adc_busy as input ,it gives error (telling that input adc_busy is wire)...Please suggest some code so that adc_busy will be input which depends on output "trim_code" ,so that I can see adc_busy waveform.
  2. WBahn


    Mar 31, 2012
    Could you be a bit more clear in your description. Better yet, give some kind of diagram, such as a timing diagram, of what you need and also what you have tried thus far. If you have code that is throwing an error, it would be helpful to see that code.
    yagyasen likes this.
  3. yagyasen

    Thread Starter New Member

    Jun 18, 2013
    Thanx for your response :) .....problem got solved now.
  4. djsfantasi

    AAC Fanatic!

    Apr 11, 2010
    And how now did the problem get solved? For others to learn we should share.