Verilog and a HD44780 LCD module

Thread Starter

Daniel.Ferguson

Joined Mar 5, 2007
1
Hi Folks,
I'm trying to initialize and use a HD44780 LCD module that is connected to my Spartan 3A starter board from Xilinx. I've written some verilog and, presumably, correctly followed the section titled "Character LCD Screen" in their manual. http://www.xilinx.com/bvdocs/userguides/ug330.pdf

Alas, being new to Verilog and everything else, i'm hard pressed to figure how close i may *really* be :)

I've used Several Sites to help guide me, but they mostly use microcontrollers in their examples.

http://www.fpga4fun.com/TextLCDmodule.html
http://www.myke.com/lcd.htm
http://home.iae.nl/users/pouweha/lcd/lcd.shtml

here is the code i've written so far...
i have no style, and know nothing about best-practices yet...sorry. But maybe someone could give me a clue/hint or some good old fashion guidance!

Thanks!!

Rich (BB code):
`timescale 1ns / 1ps

module LCDTest1(iClock, LCD_E, LCD_RS, LCD_RW, LCD_DB);
	input  iClock;
	output LCD_E;
	output LCD_RS;
	output LCD_RW;
	output LCD_DB;
	
	wire LCD_E;
	wire LCD_RS;
	wire LCD_RW;
	wire[7:0] LCD_DB;
	
	reg 		e;
	reg 		rs;
	reg 		rw;
	reg[7:0] db;
	
	
	//Responsible for putting the data on the bus
	// and then pulsing the LCD_E line for 12 clocks
	task WriteNybble;
		input reg[3:0] nyb;
		begin		
			db[7:4]	= nyb;			
			#40 	e	= 1'b1;			
			#12 	e	= 1'b0;
		end
	endtask
	
	initial
		begin
			#100;	//Waiting for global reset to complete

			//initialize my variables
			e			=0;
			rs			=0;
			rw			=0;
			db			=8'b0000_0000;
			
			#750000;//Wait for LCD to come on line ~15 ms			
			
			//Do the initialization sequence.
			WriteNybble(4'b0011);
			#250000;//5 ms
			WriteNybble(4'b0011);
			#8000;//160 us
			WriteNybble(4'b0011);
			#8000;//160 us
			WriteNybble(4'b0010);
			#8000;//160 us
			
			//Function Set  0x28
			WriteNybble(4'b0010);
			#50;
			WriteNybble(4'b1000);
			#8000;//160 us
			
			//Entry Mode Set 0x06
			WriteNybble(4'b0000);
			#50;//1 us
			WriteNybble(4'b0110);
			#8000;//160 us
			
			//Display On 0x0C
			WriteNybble(4'b0000);
			#50;//1 us
			WriteNybble(4'b1100);
			#8000;//160 us
			
			//Clear display  0x01
			WriteNybble(4'b0000);
			#50;//1 us
			WriteNybble(4'b0001);

			
			#85000;//1.64 MS
			
			//Set Initial DD Ram
			WriteNybble(4'b1000);//sets to the first spot, upper  left
			#50;//1 us
			WriteNybble(4'b0000);//
			#8000;//160 us
			
			rs = 1;
			#50;
			//0100_0001 - write an 'A'  to the screen!!!!
			WriteNybble(4'b0100);
			#50;//1 us
			WriteNybble(4'b0001);
			#8000;//160 us
			rs=0;
			
		end
		

	//and finally, connect the wires
	assign LCD_E 	= e;
	assign LCD_RS 	= rs;
	assign LCD_RW	= rw;
	assign LCD_DB	= db;
	
endmodule
 

Dave

Joined Nov 17, 2003
6,970
Hi Daniel and Welcome to All About Circuits.

I can't help specifically with the Verilog since I've never used it, and it may seem a crazy question but does your design download and work on the Spartan board? If so, I would say you are 90% there irrespective of formatting or structure. I would also recommend you make all initialisations at the start of the code (even if the language does not require it) - you appear to have done this in a clear and well structured manner, generously comment you code for future reference (it doesn't matter how trivial the comment is, it will stand you in good stead later in the day), take extra care with your indents (improves reability and helps avoid problems later should you choose to modify the code), and some would argue make generous use of white-space (I personally don't like white-space in code, but again people suggest that it improves readability).

Dave
 

alvieboy

Joined Aug 30, 2008
1
You cannot use delays in verilog for synthesis. That is used only for simulation.

I am writing a simple LCD controller (wishbone) for my Spartan 3E and using a ZPU, so please contact me if you want it.
 
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