Variable Voltage in VHDL

Discussion in 'Embedded Systems and Microcontrollers' started by TierOne, Jul 31, 2011.

  1. TierOne

    Thread Starter New Member

    Feb 5, 2011
    Hi all,

    does anyone have any idea how i can implement a variable voltage output on the i/o pins? like say i want 2.5V or 3.5V.
  2. kavli

    New Member

    Aug 1, 2011
    Since it's all digital you can't. But of course it's not the whole truth. Actually you can, using PWM and an LP-filter. Sure, the LP-filter will now dictate how fast you can change that output. Note that you can't increase the output voltage this way, only lower it.

    -- K
  3. guitarguy12387

    Active Member

    Apr 10, 2008
    Actually, there's more truth to that than you give credit. If you want to go down to transistor level modeling, you can actually model different supply values in verilog using signal 'strength's, which I am told can be synthesized to different supply voltages. However, this will be very tool and target dependent, and i don't think it is synthesizable on fpgas. If it is, i'd guess they're just assigned logical values.

    Anyway, i'm sure this is beyond what you were hoping to do... but I had to chime in! For all (or at least... most) intents and purposes, listen to Mr. K.

    Another thing came to mind: if you are targeting FPGAs, you can often assign different I/O standards to different banks in the FPGA at configure time. In Xilinx land, you can do that in the UCF with the iostandard attribute. Check your users guides.