Using Xilinx Libraries Guides

Discussion in 'Programmer's Corner' started by drkidd22, Apr 19, 2011.

  1. drkidd22

    Thread Starter New Member

    Apr 6, 2011

    I'm new to the CPLD world and have a few questions regarding Xilinx's Libraries Guide.

    I'm using Verilog HDL with ISE v13.1 with the CoolRunner-II Dev Board.
    Basically my question is how would I use the flip-flops that are in the library.
    They have the FD (Macro: D Flip-Flop) and FD16 (Macro: Multiple D Flip-Flop).

    I couldn't find a tutorial that would show me how to use them instead of having to write each module. I couldn't find them in the Language Templates either.

    Any help will be greatly appreciated as I'm trying to use a few of the macros in the libraries.
  2. guitarguy12387

    Active Member

    Apr 10, 2008
    Are you looking to draw a schematic? They are in the 'symbol' tab when drawing your schematic.

    Flip flop is pretty easy in verilog....

    Code ( (Unknown Language)):
    2. reg q;
    3. wire d;
    4. ...
    5. always @ (posedge clk)
    6.     q <= d;
    7. ...
  3. guitarguy12387

    Active Member

    Apr 10, 2008
    Otherwise, for using those libraries, you treat them sort of like a function that you're supplied with. Just look in the library guide for the instance name.

    The lib.pdf guide provides you with vhdl and verilog example instantiations...
  4. rfordh

    New Member

    Oct 26, 2010
    Yeah, you'll want to look at the examples in the guide. For example, from the Virtex4 guide, this is given for the FDCPE element:

    Code ( (Unknown Language)):
    2. FDCPE #(
    3.  .INIT(1'b0) // Initial value of register (1'b0 or 1'b1)
    4. ) FDCPE_inst (
    5.  .Q(Q), // Data output
    6.  .C(C), // Clock input
    7.  .CE(CE), // Clock enable input
    8.  .CLR(CLR), // Asynchronous clear input
    9.  .D(D), // Data input
    10.  .PRE(PRE) // Asynchronous set input
    11. );
    You'll want to put this in your code and connect the signals you want to those ports (your signals will be the ones in the parentheses).