Using Positive edge trigger flip flops to design a JK FF with double edge trigger

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Joined Sep 7, 2011
Our professor asked us to make a JK flip flop double edge triggered using a positive edge triggered JK flip flop and some combinational circuits.. how can we do this? We had this in our exam and no one got it. Can someone help me solve this problem?


Joined Jul 17, 2007
Here is one way to do it; see the attached.

I used capacitors to couple the rising and falling edges to the bases of PNP and NPN transistors, causing them to momentarily conduct. Diodes are used to prevent excessive excursions above the supply voltage or below ground. Resistors are used to keep the transistors OFF by default.

There is certainly a more simple way to do this, but I'm in a time crunch at the moment.



Joined Mar 14, 2008
You can use an exclusive-or gate and some inverters to output a positive edge pulse on every clock transition (also called a clock doubler).

Connect one input of an exclusive-or input directly to the clock. Connect the other exclusive-or input to the clock through an even number of inverter gates. The exclusive-or will output a pulse on each clock transition with pulse width equal to the delay through the inverters. For a longer pulse width use more inverters.

Nand and Nor gates can also be used as inverters by typing all the inputs together.
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