Hi I'm new to this forum so hello all.
I'm stuck in a pretty easy 100 level circuit question, plz help.

1.The following Boolean expression can be used to test for the overflow or underflow of a computation. (2's complement encoding in this case, but I dont think it matters in this question)

z= s(3) * a(3)' * b(3)' + s(3)' * a(3) * b(3)
where s(3) is the sign bit of the result and a(3) and b(3) are the sign bits of the operands.

Question:
Design a circuit to implement this function using a 4x1 multiplexer(MUX-4 wo/en) and an inverter. Package this circuit as a component with the name "OV".


I'm looking at the default MUX-4 wo/en right now and I see S1 S0 D3 D2 D1 D0 a total of 6 port in(s) and one port out Q, have no idea how to attach them in the above boolean expression.

 

Let's start a bit more simple.

Take a 2:1 MUX. You have a select line, S, (1 bit) and two data inputs, D0 and D1, in which the output,Y, is equal to D0 if the select line, S, is 0 and it is equal to D1 if the S is 1.

Now put this in a black box and bring in two input signals, A and B, and an output signal, Y. Tie the output of the MUX to the output of the black box. Tie the S input to the MUX to the A input signal and tie B to both the D0 input of the MUX and the input of an inverter. Tie the output of the inverter to the D1 input of the MUX.

Walk through all the possible combinations of A and B and prepare a truth table. Does this look like the truth table for any of the standard 2-input logic gates?

Now repeat the exercise but tie D0 input HI, leaving all the other connections the same. What standard 2-input logic gate does this implement?

Do you see what is going on?

Can you figure out a process by which you can use a 2:1 MUX and, if needed, an inverter to implement ANY 2-input logic function? If so, then do you see how to expand that to any 3-input function by using a 4:1 MUX?

 

so I think I understand a little bit better now, I got this far, i don't know how to directly assign 0 to a pin so I used a unnamed port in and set the value to 0, I dont know if it affected my result or something did, anyway the result is very confusing
s3 a3 b3 z
0 0 0 0
0 0 1 X
0 1 0 X
0 1 1 1
1 0 0 1
1 0 1 X
1 1 0 X
1 1 1 0

can you plz tell me where went wrong?

 

What are the X's in your truth table for? Those don't match the equation for z you gave in your original post.

Your circuit looks good from a logic sense. I think the problem is that you have created to input ports and named them both "0" but then this port is not driven on the top level schematic, so it is assumed that it is "unknown". To see if this is, indeed, the problem, try tying them together to a single port named LO and then drive this port with a logic LO input. If that solves the problem, then it is just a matter of figuring out how to tie a signal HI or LO in your schematic capture software.