I read that since CPU is fast & flash is slower so when CPU send a request to read data memory from a particular address, flash can send wait cycles & after then it sends ready s/g then after CPU reads data .

Let 8051 has 2 WS
So normally like ADD instruction in 8051 is suppose 2MC. Means 24 oscillator cycle. Does that these 24 cycles has 2 WS cucles with it.

So it is time CPU takes to execute only not read the instruction.


So a program like takes cycles

ADD A,R1 /* 2MC(24 cycles) + 2WS cycles */
SUB A,B /* 2MC(24 cycles) + 2WS cycles */

 

An 8051 has no facility for inserting wait states. You cannot put the processor into an idle state for a slow device.

 

Waitstates are used on external memory of processors. If all memory(FLASH/SRAM/DRAM) is on-chip it does not need wait states or it is inserted automatically. The execution time given will show this. If an external memory interface is availbe the processor(e.g. to access external DRAM memory) usually waits for a ready signal. If it is not there it will insert another wait cycle. Please check if your 8051 has an external memory interface. If not you can only address external memory through the IO and emulation the handshake in software.

 

I read that since CPU is fast & flash is slower so when CPU send a request to read data memory from a particular address, flash can send wait cycles & after then it sends ready s/g then after CPU reads data .

Let 8051 has 2 WS
So normally like ADD instruction in 8051 is suppose 2MC. Means 24 oscillator cycle. Does that these 24 cycles has 2 WS cucles with it.

So it is time CPU takes to execute only not read the instruction.


So a program like takes cycles

ADD A,R1 /* 2MC(24 cycles) + 2WS cycles */
SUB A,B /* 2MC(24 cycles) + 2WS cycles */

The actual number of cycles depends on the instructions. For instructions that involve only internal registers, no wait states need to be inserted.
SUB A,B /* 2MC (24 cycles) */

For fetching data from RAM (ROM, etc), wait states are needed.
ADD A, R1 /* 2MC (24 cycles) + 2WS (24 more cycles) */