I am making an effort to understand word sizes, program counters, and memory size. Looking over data sheet for the PIC12F629 under "Memory Organization" in section 2.0, the datasheet states:

The PIC12F629/675 devices have a 13-bit program counter capable of addressing an 8K x 14 program memory space. Only the first 1K x 14 (0000h-03FFh) for the PIC12F629/675 devices is physically implemented. Accessing a location above these boundaries will cause a wrap-around within the first 1K x 14 space

Word size for this MCU is 14-bits wide. My understanding is that most instructions are 1 word, and a few are 2 words. The instructions reside in the program memory, which is why it is 14 bits wide. 8K x 14 means that the program memory can hold ~8,000 lines of instructions, each 14 bits wide. The Program counter is only 13 bits wide, but that's because the instructions themselves don't actually get moved into the program counter, it is just there to address the line the actual instruction resides on in the program memory? It is 13 bits wide because that is the necessary number of bits required to address up to 8K?

I think all of that is right, but I'm looking for confirmation on my understanding of it. The next question I have is, when it says that only the first 1K x 14 is implemented, what does that mean? Does that mean that this particular MCU's program memory is actually only 1K x 14 rather than 8K x 14? If that is the case, why not just specify that program memory size is 1K x 14 and use a program counter that is only 10 bits wide?

And finally, if someone could explain what is meant by "addressing a location above these boundaries will cause a wrap-around within the first 1K x 14 space".

Thank you for the help.
Ryan

 

Does that mean that this particular MCU's program memory is actually only 1K x 14 rather than 8K x 14?

Yup.

If that is the case, why not just specify that program memory size is 1K x 14 and use a program counter that is only 10 bits wide?

To limit the number of actual internal hardware designs necessary.

And finally, if someone could explain what is meant by "addressing a location above these boundaries will cause a wrap-around within the first 1K x 14 space".

The 13 bit PC is enough to address 8192 14bit-wide program memory words. Only 0-10 are used which decodes 2048 but only 1K are actually present. So.. when you try to access the upper 1K with only the lower 1K present the lower 1K is repeated. Bit 10 of the PC is ignored and treated as '0' when addressing the program memory.

Of future note is PCLATH, the goto and call instructions. Only the lower 11 bits of the 13 bit PC are encoded in the instruction itself allowing you to call/goto only within a 2048 instruction 'bank'. This is enough for memory <=2048 but for anything bigger you must MANUALLY set up PCLATH to generate the upper bits of a call/goto. In the case of CALL, you also must RESTORE PCLATH after returning. If you don't the next call/goto will take you to the previously selected bank.

Its confusing because the 13 bit PC is enough to address 8K but due to the limited space to encode addresses in the instructions the 8K must be chopped into 4 x 2K banks with PCLATH providing the 'rest' of the instruction's target address.

The fact that the program memory is 14 bits long is immaterial to its addressing save the fact that if it were longer, a bigger target address could be encoded in call/goto eliminating the banked program memory. The 18F has a 16 bit program memory width and actually uses 2 words for call / goto so it has a completely linear program memory.

Note that ALL midrange(non-18F or 'enhanced midrange' ) instructions are one 14bit word long but any that cause a jump, call or return will take an extra Tcyc, not because of using 2 program memory words but because the program memory pipeline is flushed and takes an extra Tcyc to fill again.

The skip instructions are specified at 1 or 2 cycles to account for the fact that when it skips, the CPU executes a dummy NOP to 'skip' over the non-executed instruction.

 

It only has 1K of 14 bit instruction space, I guess they designed that bit of the chip thinking there would be a version with more program memory.
It's best not to worry about it, I think the only ways to set the program counter above 1K are to intentionally change PCLATH or not have a loop so that when it gets to the end of the 1K program memory it starts back at the beginning.
The wraparound part, if you set the program counter to 1025 for example, it would execute the instruction at location 1. Everything would work as normal.

 

Thank you to the both of you for helping to clear all that up, it is truly appreciated.

 

PIC addressing is an awful mess.
Its partly due to historical reasons when they used very small micros.

I much prefer micros with linear memory.