# Understanding Logic of Problem

Discussion in 'Homework Help' started by tquiva, Dec 12, 2010.

1. ### tquiva Thread Starter Member

Oct 19, 2010
176
2
Problem:
A property of code is that one's always appear in pairs, no more no less. So for example the following sequence of bits is a valid code word:

001101100011000110

but the following code word is invalid (it has errors in 2 places):

011101100011110110

We would like to detect invalid code words by producing a single output, Z, which is true if there is one or more errors anywhere in the word, and false if the full word meets the spec. The problem is, at this point, we do not know how many bits will be in a code word.

Derive a minimum unit cell (module containing combinational logic) which will get one data bit of the code word together with whatever staging inputs are needed.

I have the solution for this problem, but I just can't seem to understand the approach taken to solve it.

The goal is to create a module that looks like this, with Di being the data bit.

I have an encoding which is:

And from this encoding, I am suppose to come up with this truth table:

Now, I am completely lost at this point. The outputs above (S1S0) were obtained from the encoding table, but I have no idea how this was done.

For example, on inputs 001, output 01 is obtained.

Do I just match S1 S0 from the enocoding table to the truth table? It matches for some inputs, but not for all.

Please help me someone? I know that after the truth table, I would just make K-Maps to get the functions, and I have no problem with that. Just understanding the logic is an issue for me.

2. ### Kermit2 AAC Fanatic!

Feb 5, 2010
4,166
1,125
The module will be looking for 1's so it should not have any reaction to a zero until a 1 is encountered. Zero's just 'clock' the two state registers with more zero's. Once the first 1 is input the first state register must see a 1, or the flag is set on the code. If the second 1 is input, then the first state register MUST see a zero, or the flag is set.

It would help if you broke down the logic further than what you have in the generic two bit shift register. Further detailed decision making logic should be included at this stage. The truth tables and gates can be further simplified after they are mapped out in long form.

3. ### thatoneguy AAC Fanatic!

Feb 19, 2009
6,357
728

This says zeros are nearly meaningless, you only need to find an unpaired 1 to fail, or 3+ ones in a row.

If the number of bits in each code were the same, this is nearly a parity generator, counting set bits, deciding if even or odd, it isn't a parity generator as that function will not state if the 1s are paired, only if the correct number of ones exist.

--EDIT: Left window open way too long, didn't see Kermit's response.

4. ### Georacer Moderator

Nov 25, 2009
5,181
1,289
What is the input D supposed to be, and what do the outputs S0 and S1 represent? Can you show a full circuit of this problem?

BTW, if I had this question I would do it very differently.