Hello. I have an LM317 in this configuration:

I have a superficial description of what this circuit, but my intension is to better understand and perhaps be able to explain the problem analytically.
By reading the datasheet I have seen that this requires an integrated voltage-Vout Vadj to 1.25V. Also attempts to minimize the output current from the ADJ pin. But how can I analyze everything?

Here is the description that I have the circuit:
"Regulator LM317 is configured as a constant current regulator. MOSFET Q3 hanges the current from LM317 to a voltage, which in turn sets a bias voltage at the gate of another MOSFET equal to Q3. The advantage here is that Q2 will automatically adjust the gate bias to the other MOSFET as needed to correct for ambient temperature effects."

Thanks

 

http://www.soe.ucsc.edu/classes/cmpe123a/Fall09/NotesAndPapers/Power Supply Design/AN-1148.pdf

 

Grazie per il link, ma non ho ben capito qual'è la parte che dovrebbe interessare il mio caso.

 

Hello,

Please use only english here.
That way others can also understand what you have to say.

Translated with google:
Thanks for the link, but I did not understand what the party should be of interest to my case.

Bertus

 

Hello,

Please use only english here.
That way others can also understand what you have to say.

Translated with google:
Thanks for the link, but I did not understand what the party should be of interest to my case.

Bertus

I think the translation is "Thanks for the link but I have not understood well (or did not understand) what part should be of interest to me".

Of course my Italian is really horrible.

 

There is not enough information shown on the schematic.

The combination of R9+R13 must be in a range of 0.8333... <= (R9+R13) <= 125 Ohms, or the LM317 will not provide guaranteed regulation.

The current flow from the ADJ terminal is only about 40uA to 120uA. I don't see a need to minimize it.

 

Hello,

Where did you get the information about Q2 and Q3?
Seeing the schematic it shows no Q2.

Bertus

 

This appears to be the bias side of a current mirror. Q2 (not shown) is probably the transistor that provides the output current. The gate would be connected to the node named "bias", the source would connect to GND, and the drain would be the output. it will only work well if Q2 and Q3 are matched.

 

Hello,

Excuse me for Italian. I help with a translator and I confused the text.

Where did you get the information about Q2 and Q3?
Seeing the schematic it shows no Q2.

Here is the circuit in question:

At the gate of the transistor in the low frequency of 13.56MHz there is a sine wave. The regulator circuit makes sure that there is always a step of 3.6V in the gate at the bottom and also ensures (through Q2) that the temperature changes the voltage is varied accordingly.

What I do not understand is: what changes the voltage variation for each grade? Is there a way to get a formula that links the voltage to the temperature?

P.s. The transistor are both MOSFET IRF510 (Vishay).

Sorry for my english ;D