Hello,
for my Electronic Circuits and Devices lab, I have to design a two stage amplifier using either bipolar or FET transistors or a combination of both, where I have to select suitable transistors capable of providing a voltage or a power gain of at least 100dB and covering frequencies from 100Hz to 10MHz.

In the course we only covered voltage gain so I first thought of looking through the voltage gain for the configurations we looked at in class and then divide the gain so that the product of the gain of both stages will give me the desired gain. However, looking through the different configurations such as the voltage divider common emitter or the fixed bias common emitter, the value of the voltage gain derived is always given with a minus sign for example for a voltage divider configuration Av = -Rc/re which means I'll have a negative gain! Please help me figure out what configuration to choose and why, and how will I get the gain I want.
The professor gave us a hint to use a buffer or common collector (emitter follower) stage in the design, but I don't exactly understand why.

Also, I have no idea how to deal with the bandwidth provided. Should I use the equations for the lower cut-off and higher cut-off frequencies. We studied that we calculate three lower cut-off and the dominant is the biggest value; and to calculate two higher cut-off frequencies for input and output where the dominant one is the lower. How will I use this here?

I'd appreciate if someone can "enlighten" me because I am seriously confused and the deadline is approaching.
Thank you (hope it was clear enough)

 

http://www.sentex.ca/~mec1995/tutorial/xtor/xtor8/xtor8.html

 

One of the very big advantages of using FETs for broad band amps is that the value of the coupling caps will be many magnitudes lower than BJTs. On the other hand BJTs will require relatively large caps @ 100Hz but these large caps @10MHz will be problematic. Then again you could build a DC coupled BJT amplifier but it will be far more difficult to design.

 

Negative gain doesn't mean the gain is fractional (less than 1). Negative gain simply means the amplifier is inverting. The product of two "negative gain" amplifiers is positive gain, which simply means that it will be noninverting.

 

Hello all, thanks for the replies,,,

Can you please check this circuit? the gain when simulated gives me 93 which is totally okay for me! but the lower and upper cutoff frequencies are wrong (bandwidth) ,,, can you please suggest some changes in the values of the resistors or capacitors in order to adjust the bandwidth

Thanks!

 

First off, a 741 @ 100MHz!?

 

The 43 years old 741 opamp has trouble with frequencies above only 9kHz.
But since you didn't power the opamp nor bias its input then it won't work anyway.

The transistors are biased wrong so they are almost saturated.

 

You're also using very large electrolytic bypass and coupling caps. As I stated earlier, large caps will be problematic as the frequency climbs. At 100MHz a 10uF cap will include a highly inductive component and your 1000uF bypass caps will do little to bypass anything.

 

I seriously doubt that your instructor will allow you to include an op amp.

Hello,
for my Electronic Circuits and Devices lab, I have to design a two stage amplifier using either bipolar or FET transistors or a combination of both, where I have to select suitable transistors capable of providing a voltage or a power gain of at least 100dB and covering frequencies from 100Hz to 10MHz.

I think you meant that the gain should be 100, not 100dB. A voltage gain of 100dB is 100,000!

 

CDRIVE, the upper cutoff is 10MHz, not 100MHz.

 

CDRIVE, the upper cutoff is 10MHz, not 100MHz.

Oops I missed that but even at 10MHz I would think with those caps are a problem.

Chris

 

Hello,,

CDRIVE and Audioguru ; I really don't know much about circuit elements and I look at them as merely numbers :s However I used another circuit for my project demonstration which was yesterday however I used a BJT buffer (emitter follower stage in between two identical 50 dB gain stages) and the upper cut-off was at 1MHz which I think was expected but I don't actually know why?!

Ron H; it is 100dB and he did say it was very big! but I actually got it eventually !

Thanks all for the replies

 

A single transistor with no load has a max voltage gain of about 200 (+46dB).
Two transistors with a buffer in between so the first one has no load will have a voltage gain of about 40,000 (+92dB).

 

I thought you were restricted to two stages. At least that's what the topic title says.