# two-stage JFET / BJT common-source / common-emitter amplifier

#### stevy123

Joined Nov 19, 2007
61
Hi all

Just wondering could anyone help me with this circuit.

I am trying to work out values for Re and Rc but am confused.

i have worked out the other resistor values by

let Vg = Vcc/10 10/3 = 3.3v
let Vgs = vp/2 -2/2=-1v

Vs = 3.3 +1 =4.3v
let Id=Is= 1 mA
Rs= 4.3/1mA = 4.3K

let Vd = 2Vcc/3 = 2x10/3 = 6.66v

Rd= 10 -6.6/1mA = 3.4K

R1 + R2 need to be as large as possible. R1 should be twice R2

so let R1= 2M so R2 = 1M

Also

JFET
Vp = -2 V
IDSS = 4mA
VA = 100 V

BJT
IC (rated) = 1 mA
b = 150 (b = beta)
VA = 100 V

Could someone tell me if i have worked out the values correctly and how to go about working out Re and Rc

Many thanks
steve

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#### Ron H

Joined Apr 14, 2005
7,014

#### rwmoekoe

Joined Mar 1, 2007
172
what is the supposed bandwidth of it?
the gain?
is the linearity critical at all?
the circuit lacks negative feedback loop for linearity and stability.
the gain will depend too much on frequency, temperature, beta, and all.

#### stevy123

Joined Nov 19, 2007
61
Hi Ron H

With regards to what

let Vg = Vcc/10 10/3 = 3.3v means

It is the working out for Vg (the voltage at the gate)

which is vcc/3 and equals 3.3v. Sorry typing mistake.

Thanks
Steve

Can you advise on how to work out the values of Re and Rc

#### Ron H

Joined Apr 14, 2005
7,014
JFETs have such sloppy specs, I don't see how you can have a predictable quiescent point for this circuit. Have you been assigned this circuit topology, and you have to pick component values, or did you choose the design yourself?
Do you have part numbers for the transistors?

#### rwmoekoe

Joined Mar 1, 2007
172
you've already put the 100uf cap at the emitter. it's leaving the working re as internal rbe wich is very small and dependant on temperature, frequency, etc.
let's say we must go on with that, we still have to decide the gain.
if you want the gain to be 10, and the internal rbe at room temperature is around 60 ohms, then the rc should be 600 ohms and the re can be calculate to give the optimal dc level for the output. it depends on the dc level of the previous stage.