The first problem has an input w and output z. z is 1 when the input w previous 4 values are either 1111 or 1010 overlapping patterns are allowed. Here is some test inputs and their outputs:
w = 0101111010100111110
z = 0000000100101000011
I need to
a) Show state table.
b) Minimize to determine a non-redundant state table states.
c) Write the VHDL code.
a) From the outputs I can see that this is a moore fsm. I have the state table and diagram here:
b) When I attempt to minimize this I don't find any redundant states:
P1 = (ABCDEFGH)
P2 = (ABCDFG)(EH)
P3 = (ABCF)(G)(D)(E)(H)
P4 = (A)(B)(C)(D)(E)(F)(G)(H)
c)When I simulate my vhdl code using a functional simulation my machine acts like a mealy machine which I don't want and I am not sure why. I am using quartus to do my simulation. The states are assigned values instead of auto assigned values because I used them values to make a karnaugh maps to draw the FSM.
VHDL:
Here is the sim wave form:
The second question is similar to the first but in need to make a fsm that has three inputs w1, w2, w3 that if equal for any three consecutive cycles z will be 1. Here are some test inputs and their outputs:
w1 = 0110111000110
w2 = 1110101000101
w3 = 0110100000110
z = 0001100001100
I need to:
a) Show state table.
b) Write vhdl code.
a) From outputs this is a mealy fsm my state table and diagram are:
To get x I made a circuit to see if w1, w2, w3 are equal (in vhdl code).
b)My problem with this is my vhdl code seems to have a similar problem as the first question and I can't figure it out. I let the states be auto assigned this time.
VHDL:
This results in this sim output which seems to be making z = 1 at two not three:
w = 0101111010100111110
z = 0000000100101000011
I need to
a) Show state table.
b) Minimize to determine a non-redundant state table states.
c) Write the VHDL code.
a) From the outputs I can see that this is a moore fsm. I have the state table and diagram here:
b) When I attempt to minimize this I don't find any redundant states:
P1 = (ABCDEFGH)
P2 = (ABCDFG)(EH)
P3 = (ABCF)(G)(D)(E)(H)
P4 = (A)(B)(C)(D)(E)(F)(G)(H)
c)When I simulate my vhdl code using a functional simulation my machine acts like a mealy machine which I don't want and I am not sure why. I am using quartus to do my simulation. The states are assigned values instead of auto assigned values because I used them values to make a karnaugh maps to draw the FSM.
VHDL:
Rich (BB code):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mfsm IS
PORT(Clock, Resetn, w: IN STD_LOGIC;
z :OUT STD_LOGIC);
END mfsm;
ARCHITECTURE Behavior OF mfsm IS
SIGNAL y_present, y_next : STD_LOGIC_VECTOR(2 DOWNTO 0);
CONSTANT A : STD_LOGIC_VECTOR(2 DOWNTO 0) := "000";
CONSTANT B : STD_LOGIC_VECTOR(2 DOWNTO 0) := "001";
CONSTANT C : STD_LOGIC_VECTOR(2 DOWNTO 0) := "010";
CONSTANT D : STD_LOGIC_VECTOR(2 DOWNTO 0) := "011";
CONSTANT E : STD_LOGIC_VECTOR(2 DOWNTO 0) := "100";
CONSTANT F : STD_LOGIC_VECTOR(2 DOWNTO 0) := "101";
CONSTANT G : STD_LOGIC_VECTOR(2 DOWNTO 0) := "110";
CONSTANT H : STD_LOGIC_VECTOR(2 DOWNTO 0) := "111";
BEGIN
PROCESS(w, y_present)
BEGIN
CASE y_present IS
WHEN A =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= B;
END IF;
WHEN B =>
IF w = '0' THEN y_next <= F;
ELSE y_next <= C;
END IF;
WHEN C =>
IF w = '0' THEN y_next <= F;
ELSE y_next <= D;
END IF;
WHEN D =>
IF w = '0' THEN y_next <= F;
ELSE y_next <= E;
END IF;
WHEN E =>
IF w = '0' THEN y_next <= F;
ELSE y_next <= E;
END IF;
WHEN F =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= G;
END IF;
WHEN G =>
IF w = '0' THEN y_next <= H;
ELSE y_next <= C;
END IF;
WHEN H =>
IF w = '0' THEN y_next <= A;
ELSE y_next <= G;
END IF;
WHEN OTHERS =>
y_next <= A;
END CASE;
END PROCESS;
PROCESS(Clock, Resetn)
BEGIN
IF Resetn = '0' THEN
y_present <= A;
ELSIF(RISING_EDGE(Clock)) THEN
y_present <= y_next;
END IF;
END PROCESS;
PROCESS(y_present)
BEGIN
CASE y_present IS
WHEN E =>
z <= '1';
WHEN H =>
z <= '1';
WHEN OTHERS =>
z <= '0';
END CASE;
END PROCESS;
END Behavior;The second question is similar to the first but in need to make a fsm that has three inputs w1, w2, w3 that if equal for any three consecutive cycles z will be 1. Here are some test inputs and their outputs:
w1 = 0110111000110
w2 = 1110101000101
w3 = 0110100000110
z = 0001100001100
I need to:
a) Show state table.
b) Write vhdl code.
a) From outputs this is a mealy fsm my state table and diagram are:
To get x I made a circuit to see if w1, w2, w3 are equal (in vhdl code).
b)My problem with this is my vhdl code seems to have a similar problem as the first question and I can't figure it out. I let the states be auto assigned this time.
VHDL:
Rich (BB code):
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY mealy IS
PORT(Clock, Resetn, w1, w2, w3 :IN STD_LOGIC;
z :OUT STD_LOGIC);
END mealy;
ARCHITECTURE Behavior OF mealy IS
TYPE State_type IS(A,B,C);
SIGNAL y: State_type;
SIGNAL x: STD_LOGIC;
BEGIN
x <= ((w1 AND w2 AND w3) OR ((NOT w1) AND (NOT w2) AND (NOT w3)));
PROCESS(Resetn, Clock)
BEGIN
IF Resetn = '0' THEN
y <= A;
ELSIF(Clock'EVENT AND Clock = '1') THEN
CASE y IS
WHEN A =>
IF x = '0' THEN y <= A;
ELSE y <= B;
END IF;
WHEN B =>
IF x = '0' THEN y <= A;
ELSE y <= C;
END IF;
WHEN C =>
IF x = '0' THEN y <= A;
ELSE y <= C;
END IF;
END CASE;
END IF;
END PROCESS;
PROCESS(y,x)
BEGIN
CASE y IS
WHEN A =>
z <= '0';
WHEN B =>
z <= '0';
WHEN C =>
z <= x;
END CASE;
END PROCESS;
END Behavior;
