# Two 4-bit Binary Adder using SPDT switches and only 1 Full Adder Circuit

#### arwayeyen

Joined Mar 1, 2012
2
Title says it all. I need help in designing a circuit that has two 4-bit binary adder using SPDT switches. The catch is to make this with just 1 Full Adder circuit. If anyone could please help me out with this one along with a diagram, that would be great.

#### Georacer

Joined Nov 25, 2009
5,182
I imagine this is homework. I moved it to the right place.

Can you elaborate a bit more?

Must the two results calculate simultaneously?
How many bits does the full adder have?

A full question repost would be helpful.

#### Kn0x_14

Joined Mar 2, 2012
6
we also have the same problem
input:two 4 bit binary numbers implemented by SPDT switches
output: Sum shown through LEDs
the circuit must contain only one full adder
thanks...

#### Georacer

Joined Nov 25, 2009
5,182
I imagine you want the following:

Use a 1-bit full adder in a sequential circuit to process the input digits step by step. You will need 4 cycles to process the whole input and some kind of storage, ie shift register.

But I don't see how it can be done with *only* one full adder.

As I said, repost the original homework question.

#### Kn0x_14

Joined Mar 2, 2012
6

Input: 2 4-bit binary numbers implemented by SPDT switches
Output: Sum shown through LEDs

Note: Your circuit must contain only ONE (1) Full-Adder circuit and provide me a schematic diagram.

NOTE:

You will use a single (ONE) FULL-ADDER Circuit

#### Georacer

Joined Nov 25, 2009
5,182
Ok, this is a bit fuzzy. What is the context of your course at the moment? Are you still at the basic logic functions (addition, Boolean algebra) or have you reached sequential circuits?

I 'd like to interpret the lack of a bit width specification for the full adder as you being able to use a 4-bit adder, like the 7483 IC.

On the other hand, when referring to a full adder, we usually mean a 1-bit unit. But with only one 1-bit unit, this 4-bit operation is impossible.

#### Kn0x_14

Joined Mar 2, 2012
6
yes we're already studying sequencial logic

#### Georacer

Joined Nov 25, 2009
5,182
Ok. Then could it be that your professor wants to use a 1-bit Full Adder, which you will use to add the two input numbers one bit pair at a time?

That calls for two shift registers as input buffers and a shift register for the output storage.

Consider this option, but keep in mind that it call for three additional ICs, plus another to provide D-Flip Flops to create a functional pipeline.

#### Kn0x_14

Joined Mar 2, 2012
6
can you please provide me a schematic diagram for that problem? because we have to submit our circuit tomorrow if it is possible.tnx

#### Kn0x_14

Joined Mar 2, 2012
6
sir Geo and sir Bert thank you for all your advice it helps me a lot...