Hello all,
I am trying to find a switching power loss on MOSFETs
This is what I tried initially.
When Vgs is less than Vth, the drain current is 0 and Vds=VDD. No power is lost.
When Vgs crosses the threshold, the FET starts to conduct a current and Vds starts to drop simultaneously. Power loss is a product of Id and Vds.
When the FET enters a triode or linear region, Vds=0 (assuming an ideal FET) and power loss is=0
I tried a simulation on LTspice with a random FET and it showed the same result.
But I found Vishay's app note that shows different turn-on waveform in Fig. 4
Their waveform shows Vds doesn't drop until the drain current reaches its final value.
How is it possible for Vds to stay at VDD when Id≠0?
What is holding Vds to VDD? and is my circuit different from Vishay's?
Thank you
I am trying to find a switching power loss on MOSFETs
This is what I tried initially.
When Vgs is less than Vth, the drain current is 0 and Vds=VDD. No power is lost.
When Vgs crosses the threshold, the FET starts to conduct a current and Vds starts to drop simultaneously. Power loss is a product of Id and Vds.
When the FET enters a triode or linear region, Vds=0 (assuming an ideal FET) and power loss is=0
I tried a simulation on LTspice with a random FET and it showed the same result.
But I found Vishay's app note that shows different turn-on waveform in Fig. 4
Their waveform shows Vds doesn't drop until the drain current reaches its final value.
How is it possible for Vds to stay at VDD when Id≠0?
What is holding Vds to VDD? and is my circuit different from Vishay's?
Thank you
