TTL Window Shaper

Thread Starter


Joined Aug 18, 2007
Hello everyone,

I am a chemist working on creating a digital photon counting system for use with circular dichroism (if curious, In our system, we have a photoelastic modulator that generates a TTL signal of 50 kHz. When the signal is high, this corresponds to the output of left handed photons. When the signal is low, right handed photons. Now, we don't want to measure all the time when the signal is high or low. Instead, we want a "sweet spot", which is a 50% window centered around the middle of the high signal, and likewise with the low.

So I'd like to generate a pulse that will act as a trigger for our photon counter. Luckily, with the parameters I described, this is essentially doubling the frequency of the TTL signal to 100 kHz and phase shifting by 2.5 microseconds.

original 50 kHZ signal
0 - 10 microsec HIGH
10 -20 microsec LOW

is converted to 100 kHZ, phase shifted by 2.5 microseconds
2.5-7.5 12.5-17.5 microsec HIGH (two windows generated)
rest of the time LOW

Afterwards, I was going to use digital logic to parse the two windows between two different counters.

I have Googled "TTL Frequency Doubler" and "Frequency Delay" and will try to implement these circuits. But is there anything that can be suggested that will deal with both issues at once (rather than build one, then the other)? Also, my biggest concern is how to achieve matching up the original and new signals, so that the new pulse corresponds exactly with the original. For instance, what sort of unintentional delays might there be? Times like these I wish I could go back to school for electronics!

Any help is much appreciated. :)


Joined Jan 28, 2005
Perhaps it would advance the discussion a bit further if you could sketch, scan and then post a simple diagram of what you are trying to achieve. Use PDF formatted file if possible.



Joined Apr 20, 2004
A different methodology would be to use the quartz element drive signal as a trigger. An external oscillator would be gated to a counter at that time (using the positive drive signal as an example). The counter would accumulate until the count reaches a preset, whereupon a second counter, driven by the same oscillator, becomes active for another preset interval.

The first count would delay sampling the signal until the sweet spot arrived, the second interval would gate the signal sampling for the duration of the sweet spot. The external oscillator frequency would need to be high enough such that timing granularity is small enough to allow the intervals to be defined with sufficient accuracy. 10 MHz might be sufficient.

A similar process, using the same oscillator, would act on the negative drive interval.

If the polarization signal is to be dititized, an I/O card with both the A to D converter and on-board timers might be able to do the trick.