ttl NAND gate

Thread Starter

rainaby

Joined Nov 6, 2011
9
how can we assume that Vce(sat) is the operating condition for all the transistors in a ttl nand gate?? it should depend upon the voltages being applied but we ourselves assume it as such while explaning its operation.
 

crutschow

Joined Mar 14, 2008
23,527
Logic signals are fixed levels of a logic 1 or logic 0. Normally the logic high level is above the minimum required for logic 1 and logic low is below the maximum allowed for logic 0. If the voltages are between those two levels then the gate output level is undefined.
 
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