Need help designing TTL logic for attached timing diagram.
First edge of Input A signal should always trigger the output high (=1).
The second (and not the first) edge of Input B signal (during output = 1) should lower the output again (=0). Please help !
First edge of Input A signal should always trigger the output high (=1).
The second (and not the first) edge of Input B signal (during output = 1) should lower the output again (=0). Please help !
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