why is a timebase of 800ns weird?

I can't recall using any scopes that didn't use a 1, 2, 5 sequence.

 

It's just possible that all the parts from this lot have the same mistake

If the resistance of the middle resistor making up the potential divider inside the 555 (which establishes the thresholds for the chip's comparators) were too high by ~20%, that could account for the frequency reduction which the TS is experiencing. Perhaps the batch of ICs is factory rejects.

 

Would be nice to de-cap one to have a look at the die.

Time to get out the quinta-focals

 

Would be nice to de-cap one to have a look at the die.

Time to get out the quinta-focals

Would be interesting, but "quinta-focals" sounds too complex for this undergraduate

 

Would be interesting, but "quinta-focals" sounds too complex for this undergraduate

It's an old person's joke. My eyes just are not what they used to be.

 

It's an old person's joke. My eyes just are not what they used to be.

Makes me worry what kind of focals I would need at your age if I'm struggling to read the text on chips right now.

 

Chips are a lot harder to read now than they used to be and that isn't just because my eyes are older.

 

My eyes were pretty good until the lenses got rigid (could not focus) and I needed trifocal glasses for about 15 years. Then the lenses clouded into bad cataracts and blinded me. Cataracts surgery replaced the original lenses in my eyes with synthetic lenses and made my vision perfect.

 

I suppose the parts might be useful if you redo the formulas for on time and off time by taking the revised threshold points into account. It's just possible that all the parts from this lot have the same mistake: intentional or otherwise.

So I setup the following circuit which is supposed to produce a 50% duty cycle adjustable frequency 555 timer(https://www.electronics-tutorials.ws/waveforms/555_oscillator.html).
This is because I noticed the error tended to increase the higher the intended frequency was. So I set this circuit to 5 different frequencies, and at each I measured the Duty, trigger voltage, Threshold Voltage and the total resistance between pin 2 and 3. Then for each, I calculated the theoretical value of frequency that the resistance should have produced, then calculated the percentage error, and plotted it against intended frequency:
With the graph I can select a frequency, find the error, then account for this in the resistor values. I've attached the excel document incase anybody wanted to have a closer look.

 

Where did you get that circuit? It doesn't give a 50:50 mark:space squarewave, because C charges through R1 and R2 in parallel and discharges only through R2, with the current through R1 being subtracted from the discharge current.
If R2 is larger than 50k it won't oscillate at all.
It will give a 50:50 mark:space squarewave on a CMOS 555 if you delete R1, and pretty close to 50:50 on a bipolar 555.

 

Where did you get that circuit? It doesn't give a 50:50 mark:space squarewave, because C charges through R1 and R2 in parallel and discharges only through R2, with the current through R1 being subtracted from the discharge current.
If R2 is larger than 50k it won't oscillate at all.
It will give a 50:50 mark:space squarewave on a CMOS 555 if you delete R1, and pretty close to 50:50 on a bipolar 555.

You are right. Basically the 120k resistor has to be high enough that it has little effect on the charging, you can see how much it effects it by how much the measured duty cycle differs from 50%. So yeah this is incredibly rough as I didn't account for that in the theoretical frequency, its just to show that the error is related to the frequency, if I were actually going to try use these chips, I'd do much more measurements, and you are right, I should use a proper 50% duty circuit for something like that

 

To turn your maths upside down . . . .
Does the calculated time period differ from the observed time period by a constant amount, by any chance?

 

Your capacitor value is too high, the resistor value is too low and the supply voltage is also too low.

The datasheet of the Intersil ICM7555 (it is a Cmos 555 like your TS555) shows that its output resistance with a 5V supply is 2.5V/4.5mA= 556 ohms to pull-up and is 2.5V/30mA= 83 ohms for it to pull-down. That is "typical" and yours could be worse.

 

Your capacitor value is too high, the resistor value is too low and the supply voltage is also too low.

The datasheet of the Intersil ICM7555 (it is a Cmos 555 like your TS555) shows that its output resistance with a 5V supply is 2.5V/4.5mA= 556 ohms to pull-up and is 2.5V/30mA= 83 ohms for it to pull-down. That is "typical" and yours could be worse.

Ah nice thanks for the heads up I completely ignored the output impedance, I didn't realise it was that high for a CMOS 555, that will definitely cause some significant error. Guess I'll have to stop trying to cut corners and build a different circuit with a floating output or get some smaller capacitors so I can match the output better.

To turn your maths upside down . . . .
Does the calculated time period differ from the observed time period by a constant amount, by any chance?

I'll have a look at that after building a better circuit.

 

By the way, in that "50% duty cycle" circuit you can take the output from the Discharge pin (7) with a pullup to prevent loading and affecting the frequency. And that minimum resistor might need to be larger than 1.5K.

 

So I got a TI TLC555, put in the original circuit and got a freq of around 170kHz, which is more reasonable. A lot more interesting though is this section I found in this datasheet(see attached page 17)

The formulas (1-7) (duty cycle/frequency for astable multivibrator) do not account for any propagation delay times from the TRIG and THRES inputs to DISCH output. These delay times add directly to the period and overcharge the capacitor which creates differences between calculated and actual values that increase with frequency. In addition, the internal on-state resistance ron (what I think Alec_t was talking about) during discharge adds to RB to provide another source of timing error in the calculation when RB is very low. The equations below provide better agreement with measured values. The formulas Equation 8 represent the actual low and high times when used at higher frequencies because propagation delay and discharge on resistance is added to the formulas. Because the formulas are complex, a calculation tool, TLC555 Design Calculator can be used to calculate the component values.

That calculation tool is also attached, and I inputted my frequency(200kHz), duty cycle(0.58) and capacitor(1nF) values and got this:
The calculated resistance values vary significantly from my values, and building this circuit, both the TI timer and the suspect ones produced signals within the Min and Max of that table. This explains a lot but in summary:

• For TLC555 timers the classic equations do not hold at higher frequencies and the overcharging of the timing capacitor is expected.
• If I want to build a circuit like this again, I will use this excel document, or just calculate some rough values, then use some pots to find the sweet spot. This isn't really an issue, as to my knowledge, if I wanted to get a proper accurate oscillator, a 555 is not the way to go.
• As a lot of you were recommending (thanks btw) decrease the timing cap, and increase the resistors, as the lower the value of RB the greater the error the internal resistance causes

 

Aren't the min amd max frequency the wrong way round in that table?

 

Aren't the min amd max frequency the wrong way round in that table?

Yeah just some superficial error. I would guess its because the maximum column would generate the minimum frequency (maybe haven't looked at the equations yet), and the creator just put the frequency they calculated from a certain column in the same column by mistake.