Try to solve this Sample & hold Circuit!!!

Thread Starter


Joined Oct 3, 2009
Please help me to solve this Sample & Hold Circuit based problem. I tried to do this problem but i didn't get the result. I am preparing for an exam, this question is one of the previous question. Please suggest the method to solve this question as soon as possible. The question and circuit diagram is shown below.
Note: This question is not simple, it is coming under analog teaser section.Please try to give correct answer/method.otherwise don't comment!


"Consider the following sample-and-hold circuit :

VOFF is the intrinsic offset of the comparator modeled at its input.

State the value of VIN for which VOUT will go high during the hold (H) phase. "

Last edited:


Joined Apr 20, 2004
We are willing to help in areas of non-understanding, but also do not wish to simply give you the answer. What attempts have you made?


Joined Apr 20, 2004
From the forum notice -


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