# Trouble with trying to make a two stage amplifier :(

#### sitech

Joined Jul 3, 2008
23
I've been trying to build a two stage amplifier with transistors.

I've made a one-stage amplifier and it works as expected (I'm using GNUCAP and gEDA), when I then try to stick an additional stage onto the output of the first stage, I get distortion.

My idea was to have a resistor on the emitter with a capacitor in parallel, so the AC would be amplified, but the DC would have a gain of only 1. This worked fine with the first stage.

The second stage, with the transistor base connected to the output of the first stage, has an identical setup.

However, the second I plug the second stage in, when I look at the base voltage, instead of getting a nice sine wave (thats what i've been testing it with), I get a weird stepped graph. I'll try and get a picture.

Here is my circuit:

Note, there is normally a capacitor of 9 nF on the second stage with a 4.5k resistor in parallel (instead of the 1k) , just my last test was to see what happened if I removed it.

The base output looks like this:

My thoughts is that it good be input and output resistance, but I'm not sure.

I've also tried putting in a resistor in between the base of Q2 and the collector of Q1, with no beneficial effect. I only did it because I've seen it in other two stage amplifiers, but I have no idea why they did it!

Any help would be much appreciated, I've been pulling my hair out for over a day now!

NOTE: R3 is meant to be 4.5k... whoops! I'll fix that up soon.

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#### roddefig

Joined Apr 29, 2008
149
While there are others on this forum who are more knowledgable than I when it comes to analog electronics, have you accounted for the loading effect of the second stage?

I believe the correct formula for the input resistance of the second stage would be $$R_i = (\beta + 1)(r_e + R_E)$$

#### sitech

Joined Jul 3, 2008
23
See thats what I thought it might be.

But the output impedence of the first stage is 4.5 k (well, yes the resistor is 7.5k, but thats an error on the diagram).

In the original circuit where the second stage resistor was 4.5k and bypassed with a 9 nF capacitor I calculated (if my logic is correct).

For DC:
$$R_i=4.5k\Omega\times100=450k\Omega$$

for AC:
$$Z_i=\frac{1}{2\pi\times40KHz\times9\times10^{-9}pF}\times\beta=450\Omega\times100=45k\Omega$$

Both of which are at least 10x greater than the output impedence of the first stage!

#### Wendy

Joined Mar 24, 2008
22,138
Your base resistors (R1 and R2) are way too large for the emitter resistance (R4). Figure a beta of 50, then your DC base input resistance is going to be in the neighborhood of 500KΩ (R4 X Beta). Try dropping R1 and R2 down a factor of 10 or so.

Like the schematic, you are one of the few...

#### sitech

Joined Jul 3, 2008
23
See that shows that I don't understand input and output resistance.

What I got from the book I'm reading is that you want the input resistance to each stage to be high, but the output resistance to be low...

I tried dropping them by a factor of 10 and also 100 however I still got the same result for the base.

Here is the circuit I tested.

#### Wendy

Joined Mar 24, 2008
22,138
What is the input P-P AC voltage (I'm thinking around 2mv)? Also, what is the frequency?

Did you look at your DC voltages before and after? Betcha you saw a lot of change. The transistor needs to be firmly in its linear region for it to be linear. The DC biasing is important for this, so you have to look at your DC parameters before you look at the AC.

I'm going to be looking at this a bit more, it's the kind of problem I like. BTW, I use the computer between my ears to simulate, when SgtWookie gets here he'll be a bit more use than I. You might think about posting your files for review.

Something else to consider, assuming 50X gain on each stage (with emitter swamping caps this isn't too unreasonable) then 2mv X 50 = 100mv, 100mv X 50 = 5V. I don't think the DC biasing will allow this kind of swing.

OK, I'm not using a calculator here, so this is off the cuff. The base of the first transistor is almost 5V, so you have 4.3V on the emitter. This means the collector of Q1 is going to be 4.7V. The emitter of Q2 will be around 4V, which means the collector of Q2 is around 5V. Since the collector can't go more negitive than the emitter this would seem to present a problem.

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#### sitech

Joined Jul 3, 2008
23
Thanks for the help I'm using a 1 mv input.

okay now I'm really confused, and I'm not sure if it is a problem with the software I'm using.

I decided to fix the problem you pointed out by making the voltage divider produce 7V, thus the base of stage 1 producing 6.3V, which means the output should oscillate around 2.7V (first stage doesn't seem to exceed 0.01V). This should mean the output should oscillate around 7V.

7V is probably too high, but I thought I'd just try that as a test.

However, now when I test it without a signal (just the DC bias), it seems to not work at all as expected. R1 and R2 I have to reduce to 180 and 620 ohms to get out the proper voltage. Increasing R4 does not seem to compensate whatsoever! So basically now for some reason, instead of the output voltage being 2.7V, it seems to want to match the voltage at the emitter of 6.3V! I have no idea why it is doing this?!

#### Wendy

Joined Mar 24, 2008
22,138
Like I said, the collector CAN NOT be more negative than the emitter. Think current paths. You need to take the emitter to a low voltage, say 2 volts, and the collector will be 7V. Think in terms of current and voltage drop. R3 and R4 are going to drop the same amount of voltage, so if the emitter is 2 volts, the collector will be 9Volts (power supply) - 2volts (R3 drop), 7 volts.

BTW, this will also increase the amount of possible swing in the voltage.

This voltage will propagate through to the base of Q2, so you have to adjust for that.

#### sitech

Joined Jul 3, 2008
23
okay, I'm just going to ask you to completely ignore that last post.

Thats like the second time I've done that today!

Whoops! (embarassed)

Thanks

#### Audioguru

Joined Dec 20, 2007
11,249
Your emitter resistors have a value that is way too high and are wasting half the supply voltage.
Since the collector resistors are 4.5k then use 470 ohms for the emitter resistors.

You have the base voltage so high that the first transistor is saturated and the second transistor is almost saturated.

When the transistors are properly biased then each will have a voltage gain of about 126. The total gain of this amplifier is about 16,000 so the input should be less than 0.2mV.

Make it like this. Without negative feedback then it will be very distorted when the output level is high.

PS. Why is your schematic as a hard to see negative??

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#### Wendy

Joined Mar 24, 2008
22,138
I was just happy to see a schematic myself.

#### sitech

Joined Jul 3, 2008
23
Thanks! That worked perfectly.

Wow, I'd be stuck without everyone's help.

I just discovered that one of my problems was I was looking at the first 500 microseconds of the circuit, which doesn't seem to be indicative of the rest of the circuit. (Though I doubt I would have worked out the rest of the issues even without that impediment).

Why inverse? It was just how the program I was using (gschem) made them (I assume default colour scheme). The colour scheme you have seems a little easier. The gschem one is a similar scheme to what programs like AutoCAD uses, so maybe its a historical thing?

Thanks once again! Now for the next stage of turning it into a constant 5V (making an ultrasound water tank level meter, so basically trying to time how long it takes for a pulse to reach the reciever).

#### sitech

Joined Jul 3, 2008
23
One final question.

Could all this be achieved with an op-amp. I'm a little confused as to when you'd make a voltage amplifier using transistors and when you would use an op-amp?

#### Wendy

Joined Mar 24, 2008
22,138
Yep, one of the reasons op amps are more popular is they are MUCH easier to predict. They have their pitfalls, but overall they are much easier than a transistor to design analog amps.

Mostly this is a personal preference, and parts availablility. Transistors are a bit cheaper, but they require more parts. It's always a tradeoff. Like the old saying goes, give a man a hammer and every job looks like a nail.

#### Audioguru

Joined Dec 20, 2007
11,249
An opamp has a voltage gain of about 200,000. The high frequencies are rolled off so that with negative feedback added to reduce the gain then the opamp will not oscillate at a high frequency where the phase shift of the opamp changes the negative feedback into positive feedback.
Therefore an ordinary old 741 opamp has a frequency response to only 80Hz when its gain is 16,000. A better opamp like a TL071 will have a frequency response to 240Hz when its gain is 16,000.

Two better opamps can be used. A TL072 dual opamp can have each opanp with a gain of 126 then the total gain is 15.900 and the response is to about 20khz. The distortion will be very low.

#### sitech

Joined Jul 3, 2008
23
Thanks for the help! I need some assistance with the second stage, the rectification.

The output (voltage across R9) seems to build up gradually (over a period of 2 ms) and then tapers off at about 0.8 V, is the shape of the graph expected (going from 0 to 0.8V in 2 ms or so and then staying at 0.8V).

Finally I was looking at the signal input and is this an artifact of GNUCAP? It seems to occur at EXACTLY 10ms.

Once again, any help would be most welcome!

#### Wendy

Joined Mar 24, 2008
22,138
Is this meant to be a measurement circuit?

Don't think I'm going to be as much help on this one. It seems to me the cap C5 would have a perminant voltage develop across it, which would affect the rest of the design. How much trouble would it be to add a voltage follower transistor between Q2 and C5 to see?

#### Audioguru

Joined Dec 20, 2007
11,249
I changed some colour hues, made your negative schematic a positive and increased the black and white contrast. Then it is easy to see.

I simulated it and the rectifier/capacitor loads down the output from Q2 so much that its output begins as a small square-wave then slowly increases its amplitude as the capacitor C6 charges. It charges the fastest at 20kHz when the DC voltage across C6 is 1.0V in 1ms.

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