Transmission Gate Operation Question

Discussion in 'General Electronics Chat' started by robby991, Nov 2, 2009.

  1. robby991

    Thread Starter Active Member

    Dec 17, 2007
    Hi everyone. I have a question regarding the general operation of the transmission gate. If I have an input of, say 10 uA, will there be 10uA at the output when the Tgate is on?

    I don't understand how the Tgate works in the device point of view. How is it biased? It is not biased like a normal nMOS (source grouded, Vd bias) or pMOS. How can it pass the input current to the output when Id depends on factors like doping, W/L, and most importantly drain voltage biasing. Could someone please clarify this for me??? I am very confused. Thank you.
  2. JDT

    Well-Known Member

    Feb 12, 2009
    Yes, less leakage current. Normally, this leakage will be in the order of nano amps.

    A transmission gate usually has two MOS transistors in parallel one N-channel and the other P-channel. Because they have insulated gates there is no gate current introduced into the channel. To switch the gate ON, the gate of the N-channel is biased to the +ve supply and the gate of the P-channel is biased to the -ve supply. The on resistance of the transmission gate will depend on the voltage level of the channel between the supply rails.

    When the voltage of the channel is half way between the supply rails, both transistors will be well switched on and the resistance will be low. As the channel voltage approaches a supply rail, one of the transistors will no longer be biased on but the other will still be.

    See the data sheet of the device for a graph of resistance v channel voltage.
  3. robby991

    Thread Starter Active Member

    Dec 17, 2007
    Thanks JDT. Yes, I understand the structure of the Tgate and how it has a low resistance when there is a gate voltage applied (all MOSFETs do), but I still don't understand it from a device point of view. How is the drain current of the MOSFETs the same as the input current? Drain current depends on not only Vg but also drain voltage and W/L. I don't understand the biasing. Do you understand what I am trying to say? How would an ID-VD plot look like?
  4. Eduard Munteanu

    Active Member

    Sep 1, 2007
    The i_D = f(v_D) plot is easy to deduce. The transistor presents a low on resistance and high off resistance. So it's either almost vertical or almost horizontal. The FET acts like a switch, like an idealized saturated BJT.