hi
how to calculate the gain of collector to base bias circuit using a pnp transistor? iam using BC 558, Rb= 1M, Rc= 4.7k , Vcc= 9V.

 

Measure the current through the collector. Measure the current through the base. Divide the collector current by the base current.

 

The gain will vary with collector current and collector.

To calculate the gain of the PNP at one point, apply -9V to Rc and Rb with the transistor emitter at common (+ battery terminal). Measure the voltage across Rc and Rb. From that calculate Ib and Ic. The transistor current gain is Ic/Ib.

To determine the gains at other current levels you will need an adjustable voltage for Rb.

If you want the gain at a constant collector voltage for different collector currents, then you can apply the voltage directly to the collector through an ammeter. You then vary the Rb voltage to determine the gain at different values of collector current. Be aware that at higher collector currents and voltages the transistor power dissipation my become excessive.

 

hi
how to calculate the voltage gain of collector to base bias circuit using a pnp transistor ? iam using BC 558, Rb= 1M, Rc= 4.7k , Vcc= 9V.

Don't understand you question. What do you mean "voltage gain of collector to base bias circuit"?

Post your circuit.

 

A BC558 has a current gain of from 110 to 800 and each transistor will be different. Also, the current gain changes when the temperature changes. That is why a transistor used an an amplifier has an emitter resistor and a voltage divider providing its bias.

Your transistor has a 1M base resistor with about 8.34V across it then the base current is 8.34V/1M= 8.34uA.
If the current gain is 110 then the collector current is 0.92mA and the collector voltage is 4.7V and the transistor can be a good amplifier.
But if the current gain is 800 then the collector current will try to be 6.67mA and the transistor will be saturated and cannot amplify.

Voltage gain is the total collector load resistance divided by the internal emitter resistance of the transistor that depends on its collector current.

 

in this circuit iam using ultrasonic transducer of 40kHz. reiceving section two stage amplification given. for the pnp section, how to calculate voltage gain?

 

Instead of calculating the voltage gain of the two transistors I cheated and looked at the input impedance of a PNP 2N3906 transistor at 1mA. It is only 500 ohms. The 1M base resistor applies a little negative feedback which reduces the input impedance to about 480 ohms.
Then the gain of the first transistor is the total collector resistance (2.2k//480 ohms= 394 ohms) divided by the total emitter resistance.
Its internal emitter resistance is 26mV/Ic= 26 ohms.

Then its voltage gain is 394/(26 + 680)= 0.56 times.

The gain of the second transistor is about 4700/26= 181 times.

Then the total gain is 0.56 x 181= 101.4 times.

If it wasn't so late at night I would simulate the circuit with LTspiceIV but I am too tired.

 

1st transistor - RC coupled amplifier- iam using BC 548, hfe= 224, without byepass capacicot ,CE. therfore gain is 2.2k/680= 3.2 . is it correct?
Vcc=9V, VRc= 2.55.
2nd transistor- BC 558 , mention gain will be 4.7k/26 ? how we calculate this 26?
any equation?
in the above circuit, input to RC coupled is 200mv to 60mv. after the first stage 500mv to 150mv. but the sine wave is not perfect. wide in the negative half cycle.
after the pnp stage, output will be 9v to 5.8v. but sine get saturated when the input is 200mv to 160mv. i think gain is high.but i have to obtain a perfect sine wave. to reduce the gain i need an equation for collector to base bias circuit? i am trying to reduce 4.7k to 1k.. and 1M to 220k.. but still saturated

 

The voltage gain is equal close to.

Av = Rc/re where re = 26mV/Ic

But when you use emitter resistor the gain will drop to the

Av = Rc/(Re + re)

And both of these equations are true for NPN and PNP.

And to achieve a large voltage swing you need to set the bias point (voltage at collector) equal to 0.5Vcc.

 

1st transistor - RC coupled amplifier- iam using BC 548, hfe= 224, without byepass capacicot ,CE. therfore gain is 2.2k/680= 3.2 . is it correct?

No. Maybe you did not read my last reply.
The collector load is not only 2.2k because it is in parallel with the input of the second transistor which is about 480 ohms.
The emitter total resistance is not only 680 ohms because it is in series with the internal emitter resistance (26mV/Ic) which is about 26 ohms. So the voltage gain (loss) of the first transistor is (2.2k//480)/680 + 26)= 394/706= 0.56 times.

Vcc=9V, VRc= 2.55.
2nd transistor- BC 558 , mention gain will be 4.7k/26 ? how we calculate this 26? any equation?

Every tutorial about the voltage gain of a transistor has the equation.

in the above circuit, input to RC coupled is 200mv to 60mv. after the first stage 500mv to 150mv. but the sine wave is not perfect. wide in the negative half cycle.

Because it is driving the non-linear low impedance base-emitter diode of the second transistor.
I cannot understand the amplitude of your input. 200mV RMS or 200mV peak? 60mV RMS or 60mV peak?

after the pnp stage, output will be 9v to 5.8v. but sine get saturated when the input is 200mv to 160mv. i think gain is high.but i have to obtain a perfect sine wave. to reduce the gain i need an equation for collector to base bias circuit? i am trying to reduce 4.7k to 1k.. and 1M to 220k.. but still saturated

Of course the output is saturated. The input signal level is too high or the gain is too high. In my simulation I turned it down then measure a gain of 225 times. With the input at 200mV peak the output is trying to be (0.2V peak x 225= 45V peak but it can't since my supply is only 9V.

I added a 1.5k emitter resistor to the second transistor to reduce the gain of this circuit to 9.25 times and the output becomes a low distortion sine-wave.
Add an emitter resistor to the PNP transistor to reduce its voltage gain like the first transistor.

 

in ur previous reply, mention the input impedance of a PNP 2N3906 transistor at 1mA. It is only 500 ohms. The 1M base resistor applies a little negative feedback which reduces the input impedance to about 480 ohms.
but iam using BC 558. is it same 1mA and 480 ohms for both?

iam doing obstacle detection. when obstacle comes closer, reciver section picks 200mV peak to peak sine wave. it is fed to RC coupled and output is 500mVp-p. then it is given to pnp stage, output is 9Vp-p. but it is saturated.
input after pnp
200mV 9V saturated
180mV 8.8V sat
160mV 8.6V sat
100mV 7.6V sat
60mV 5.8V better sine

when obstacle moves far ie, 15cm distance, input is 60mV.
u mention gain about 101. therefore the above values are satisfying ?

i tried to change the Rc of pnp stage from 4.7k to 1k. therefore output is saturated in negative cycle. why saturation only in negative cycle?
iam attaching the waveform showing this. yellow colour shows saturated output after pnp. blue shows input to RC coupled.
in ur last reply, mention about adding Re. actually what happens when Re added?
this sine wave given as clock to divide by 10 counter 4017 , it divides 40kHz to 4kHz. is it required square wave to apply as clock? or any wave can be used as clock?

 

in ur previous reply, mention the input impedance of a PNP 2N3906 transistor at 1mA. It is only 500 ohms. The 1M base resistor applies a little negative feedback which reduces the input impedance to about 480 ohms.
but iam using BC 558. is it same 1mA and 480 ohms for both?

The 2N3906 has almost the same spec's as the BC558. But Fairchild says its input impedance at 1mA is only 500 ohms and my 1969 Philips databook says that a BC178B has an input impedance of 6k ohms at 1mA.
Fairchild says the input impedance of the 2N3904 is 4k ohms at 1mA so I think they are wrong about the 2N3906. I found a Philps datasheet for the BC558B. Its input impedance is 8k ohms.

i am doing obstacle detection. when obstacle comes closer, reciver setion picks 200mV peak to peak sine wave. it is fed to RC coupled and output is 500mVp-p. then it is given to pnp stage, output is 9Vp-p. but it is saturated.
input after pnp
200mV 9V saturated
180mV 8.8V sat
160mV 8.6V sat
100mV 7.6V sat
60mV 5.8V better sine

when obstacle moves far ie, 15cm distance, input is 60mV.
u mention gain about 101. therefore the above values are satisfying ?

My simulation has an input of 200mV peak and the output was saturated. With an input of 10mV peak the output was a good sine-wave and the gain was 225 times.

i tried to change the Rc of pnp stage from 4.7k to 1k. therefore output is saturated in negative cycle. why saturation only in negative cycle?

Because it did not have enough base current for a 1k collector load rersistance.

in ur last reply, mention about adding Re. actually what happens when Re added?

RE adds negative feedback. It reduces the gain because gain= Rc/Re.

this sine wave given as clock to divide by 10 counter 4017 , it divides 40kHz to 4kHz. is it required square wave to apply as clock? or any wave can be used as clock?

You have an opamp trying to saturate then it feeds the clock of the CD4017.
But most opamps cannot saturate at a frequency as high as 40kHz.
Some CD4017 ICs (Texas Instruments and maybe other manufacturers) have Schmitt Trigger shaping so they do not need a square-wave on the clock input.

 

in ur previous reply, mention about gain is 101 times by calculation. but in simulation why it is 225 times?
therefore actually gain is 225 or 101?

Rc of pnp and npn actually controls gain. but if i vary both, still the signal get sturated. why? without 1.5k as Re.

in pnp section, it is collector to base bias circuit, actually there is no capacitor across base and collector? why a 10pF capacitor used?

supply is 0 to 9V. therefore after pnp stage, amplified value goes to below zero? is it clipped becoz of that? u mention about 45V, actually this wave has both negative peak and positive peak or 0 to 45v or -22.5 to 22.5.
i know supply 9V, therefore it will saturate, thats y we cant get 45v.
but i want to know Vp-p value.

in the circuit, i am using 741 opamp as amplifier at final stage. inverting ampr, counter output will be 9V given as inverting input and 4.5v as non-inverting. therefore output will be invertiing. is it swings between positive peak and negative peak or with in 0 to 9v. i think i got it as 1.5 positive side and 4.5 negative side. but iam not sure.

 

in ur previous reply, mention about gain is 101 times by calculation. but in simulation why it is 225 times?
therefore actually gain is 225 or 101?

Because I wrongly looked at the datasheet of Fairchild's 2N3906 similar transistor that must have an error about its input impedance (it shows 500 ohms).
Philips says the input impedance of a BC558B at 1mA is 8k ohms.
Re-calculating, the total collector resistance of the first transistor is higher than I wrongly calculated so the total gain is higher than I calculated before.

Rc of pnp and npn actually controls gain. but if i vary both, still the signal get sturated. why? without 1.5k as Re.

The transistors must be re-biased if you change their Rc. But adding an emitter resistor reduces the gain better because it adds negative feedback that reduces distortion while it reduces gain.

in pnp section, it is collector to base bias circuit, actually there is no capacitor across base and collector? why a 10pF capacitor used?

It cuts high frequency gain to reduce radio interference.

supply is 0 to 9V. therefore after pnp stage, amplified value goes to below zero? is it clipped becoz of that?

The output will have an average voltage of 0V when it has an output coupling capacitor feeding a resistor to ground. Then the signal swings positive and negative. Your opamp has a coupling capacitor so the output signal swings positive and negative.
My simulation shows the output of your transistors going from +3.0V to +7.6V when its input is 10mV peak. The signal swing is more if the input level is increased but then it has distortion.

u mention about 45V, actually this wave has both negative peak and positive peak or 0 to 45v or -22.5 to 22.5.
i know supply 9V, therefore it will saturate, thats y we cant get 45v.

Correct.

but i want to know Vp-p value.

My simulation shows that with an input level of 10mV peak then the output of your transistor circuit has low distortion and swings from +3.0V to +7.6V.
When the input is increased to 20mV peak then the output swings from +1.2V to +8.8V with bad distortion.
When the input is increased to 40mV peak then the output swings from almost 0V to almost +9V with horrible distortion.
The clock input of the CD4017 counter IC needs a minimum of +2.7V to +6.3V when it has a +9V supply.

in the circuit, i am using 741 opamp as amplifier at final stage.

A 741 opamp is 45 years old. It has a minimum output of +1.5V and a maximum output of +7.5V at low frequencies when it has a +9V supply. At 4kHz its low slew rate changes a square-wave into a triangle-wave.

Why do you use an opamp at the output? What is its load?

 

opamp 741 used to drive a speaker of 8ohm. iam using inverting amplifier. therefore output voltage swing between which values?

RC coupled - npn section.
i have to draw the dc load line. i got Ic as 1.29mA. Vce= 50% of Vcc = 4.5v , hfe= 224. is required Q point will be at 4.5v? in hardware, i got Vce= 5.24v. is this Ic and Vce correct to show the bias point?

after adding Re = 1.5k, i got gain as 10. is that correct?

 

opamp 741 used to drive a speaker of 8ohm. iam using inverting amplifier. therefore output voltage swing between which values?

The 741 opamp is spec'd to drive a load that is a minimum of 2000 ohms, not 8 ohms. The inductance of an 8 ohm speaker causes its impedance to be about 40 ohms at 4kHz. The typical maximum output current of a 741 opamp is 25mA peak so the maximum output to a 40 ohm load is only 1V peak. Then the power in the speaker is only 12.5mW. Headphones are louder.

RC coupled - npn section.
i have to draw the dc load line. i got Ic as 1.29mA. Vce= 50% of Vcc = 4.5v , hfe= 224. is required Q point will be at 4.5v? in hardware, i got Vce= 5.24v. is this Ic and Vce correct to show the bias point?

You calculated when the transistors have "typical" current gain. When the current gain is higher or lower then the bias point and load line will be different.

after adding Re = 1.5k, i got gain as 10. is that correct?

The gain is 9.25 times in my simulation.

 

Is Q point can be fixed only at the centre of the load line. in the case of RC coupled. what happened if Vce= 5.36. that also 59%..
with the above Ic and Vce q point can not be at centre? how i fix the Q point?

 

Transistors have a range of current gain. Some have low gain and others have high gain even when they have the same part number.

The different gains can be made almost the same by adding negative feedback like adding an emitter resistor or having the base fed its current through a resistor connected to the collector.