I'm trying to do a homework question in which I must:

Design a circuit that uses an input clock and digital logic to generate a train of pulses of width set by a pair of 4-bit binary inputs. One input sets how long (from 0 to 15 clock units) each pulse stays in the high state, while the other sets how long each pulse stays in the low state. It's suggested by the professor that I use a J/K flip-flop and binary counters along with logic gates, as well as using the LOAD feature of the counter and counting down rather than up.

I think what this means is that each input sets the load of a counter, which in some way will make the J/K's inputs both high so that it toggles after a length of time determined by the two different 4-bit inputs. However, I can't find in the textbook or online a clear explanation of what the load input does, besides setting some value that can be reverted to.

I'd also appreciate any other hint as to what my circuit should look like: order that the data will progress, certain connections that will make it simpler, etc.

Thanks

 

It would be helpful to know the logic family, but look at the LOAD function for a 74LS161 - get the data sheet to see how it works.

Note - the function is called out as PE, parallel enable.

 

So the way I've done it now is to have each 4-bit input go to a down-counting counter. The borrow of each counter connects to the load of the other as well as a NAND gate to either the J or K input of the J/K. All chips are clocked.

This way when one counter rolls over, the other loads its input, and the J/K is either (1,0) or (0,1), so it's low or high depending on which counter is going.

I think this works, though I'm not sure about how the load works.