http://www.allaboutcircuits.com/vol_4/chpt_10/6.html

I'm unable to understand the paragh .Plzz elaborate.

(When both J and K inputs are 1, however, something unique happens. Because of the selective inhibiting action of those 3-input AND gates, a "set" state inhibits input J so that the flip-flop acts as if J=0 while K=1 when in fact both are 1)

 

Normally, I dont understand it. I just memorise the truth table by hard before the exam.

 

Normally, I dont understand it. I just memorise the truth table by hard before the exam.

Same here, I just memorized the four conditions for the J/K input combinations when clocked, set, reset, toggle and no change. How it's accomplished internally never seemed to be real important in the real world.

Lefty

 

I'll try to figure it out,if i succeed i will post the info .