# Time diagrams of flip flops,latches

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
I have the following pictures of time diagrams,but I have a problem with considering for which time diagram is e.g.for sr latch,flip flop d..
Can someone help me in my conclusion?Thanks in advance.

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#### Deleted member 115935

Joined Dec 31, 1969
0
I have the following pictures of time diagrams,but I have a problem with considering for which time diagram is e.g.for sr latch,flip flop d..
Can someone help me in my conclusion?Thanks in advance.
A nice bit of home work.

So what do you know thats different between a latch and a register in terms of their operation ?

Ans: A registers output only changes on one edge of the clock, normally the rising,
A latch, its output follows the input when the clock is "active" normally when its high, and does not change when the clock is inactive.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
A nice bit of home work.

So what do you know thats different between a latch and a register in terms of their operation ?

Ans: A registers output only changes on one edge of the clock, normally the rising,
A latch, its output follows the input when the clock is "active" normally when its high, and does not change when the clock is inactive.
Those time diagrams above are both for flip flop JK,I am just following the truth table?

#### Deleted member 115935

Joined Dec 31, 1969
0
Those time diagrams above are both for flip flop JK,I am just following the truth table?
so i dont understand the question your asking ,
may be try the homework forums

#### dl324

Joined Mar 30, 2015
13,833
Those time diagrams above are both for flip flop JK,I am just following the truth table?
Are you supposed to determine what the X and Y inputs are based on the outputs? If so, what are your answers?

EDIT: Is this homework?

Last edited:
Thread Starter

#### avalox7

Joined Aug 9, 2020
31
My question is based on above two time diagrams which flip flops are described based on the diagrams,following the truth table for flip flop jk if for example I rename the signal x and y, x=J and y=K so following the truth table for flip flop JK I get the diagram of Q and not Q.So when X=1,Y=0,C=1 q is 1 and so on.So based on my conclusion both time diagrams are desrcibed for flip flop JK.Is that correct?By the way this is not a homework some task which I have read in an old exam.

#### Deleted member 115935

Joined Dec 31, 1969
0
could you post the orriginal question from the paper in its entirety , so we can advise.

#### dl324

Joined Mar 30, 2015
13,833
So based on my conclusion both time diagrams are desrcibed for flip flop JK.Is that correct?By the way this is not a homework some task which I have read in an old exam.
I agree that the second picture is a JK FF with X=J and Y=K.

Take a closer look at the transitions with respect to the clock edges in the first picture. X and Y are not J and K, respectively.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
I think it is SR latch,x is S and R is y?So the first picture is SR latch and the second is ff JK

#### dl324

Joined Mar 30, 2015
13,833
I think it is SR latch,x is S and R is y?So the first picture is SR latch
How do you explain the fact that X changes on the rising edge of C, but Y doesn't?

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
How do you explain the fact that X changes on the rising edge of C, but Y doesn't?
Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?

#### dl324

Joined Mar 30, 2015
13,833
Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?
The first rising edge of Y causes a transition without a clock edge.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
The first rising edge of Y causes a transition without a clock edge.
So what is the correct answer for the first picture?

#### dl324

Joined Mar 30, 2015
13,833
So what is the correct answer for the first picture?
It depends. The first picture shows both outputs being HIGH at the same time for the last rising clock edge. I'd need more information regarding how the flip flops were constructed before trying to answer.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
Just see the truth table about SR latch,when clock is rising x=1=S and y=R=1 then Q is also one,the same as the diagram while in ff JK when both J and K are 1 and clock is rising the value of Q is negated of the previous so obviosly ff JK can not be.

#### dl324

Joined Mar 30, 2015
13,833
Just see the truth table about SR latch
By definition, a latch is not clocked; the inputs are level sensitive. If you cascade two latches, you can have an edge (master slave) triggered flip flop. That's why I need more information on how the flip flops are constructed.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
How you mean latches are not clocked you can clock a latch to synchronize for e.g SR synchronize with nand gates,puting the signal clock at the two first gates,when clock is not used then it is asynchronised latch.

#### dl324

Joined Mar 30, 2015
13,833
How you mean latches are not clocked
Latches are level sensitive, flip flops aren't. If you wish for me to continue this conversation, provide the details I asked for.

Thread Starter

#### avalox7

Joined Aug 9, 2020
31
In the question there is no details about the constructions of flip flops it is just asking for the following time diagrams find which flip flops or latches are described.

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