A nice bit of home work.I have the following pictures of time diagrams,but I have a problem with considering for which time diagram is e.g.for sr latch,flip flop d..
Can someone help me in my conclusion?Thanks in advance.
Those time diagrams above are both for flip flop JK,I am just following the truth table?A nice bit of home work.
So what do you know thats different between a latch and a register in terms of their operation ?
Ans: A registers output only changes on one edge of the clock, normally the rising,
A latch, its output follows the input when the clock is "active" normally when its high, and does not change when the clock is inactive.
so i dont understand the question your asking ,Those time diagrams above are both for flip flop JK,I am just following the truth table?
Are you supposed to determine what the X and Y inputs are based on the outputs? If so, what are your answers?Those time diagrams above are both for flip flop JK,I am just following the truth table?
I agree that the second picture is a JK FF with X=J and Y=K.So based on my conclusion both time diagrams are desrcibed for flip flop JK.Is that correct?By the way this is not a homework some task which I have read in an old exam.
How do you explain the fact that X changes on the rising edge of C, but Y doesn't?I think it is SR latch,x is S and R is y?So the first picture is SR latch
Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?How do you explain the fact that X changes on the rising edge of C, but Y doesn't?
The first rising edge of Y causes a transition without a clock edge.Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?
So what is the correct answer for the first picture?The first rising edge of Y causes a transition without a clock edge.
It depends. The first picture shows both outputs being HIGH at the same time for the last rising clock edge. I'd need more information regarding how the flip flops were constructed before trying to answer.So what is the correct answer for the first picture?
By definition, a latch is not clocked; the inputs are level sensitive. If you cascade two latches, you can have an edge (master slave) triggered flip flop. That's why I need more information on how the flip flops are constructed.Just see the truth table about SR latch
Latches are level sensitive, flip flops aren't. If you wish for me to continue this conversation, provide the details I asked for.How you mean latches are not clocked
by Jake Hertz
by Jake Hertz