A nice bit of home work.I have the following pictures of time diagrams,but I have a problem with considering for which time diagram is e.g.for sr latch,flip flop d..
Can someone help me in my conclusion?Thanks in advance.
Those time diagrams above are both for flip flop JK,I am just following the truth table?A nice bit of home work.
So what do you know thats different between a latch and a register in terms of their operation ?
Ans: A registers output only changes on one edge of the clock, normally the rising,
A latch, its output follows the input when the clock is "active" normally when its high, and does not change when the clock is inactive.
I agree that the second picture is a JK FF with X=J and Y=K.So based on my conclusion both time diagrams are desrcibed for flip flop JK.Is that correct?By the way this is not a homework some task which I have read in an old exam.
Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?How do you explain the fact that X changes on the rising edge of C, but Y doesn't?
The first rising edge of Y causes a transition without a clock edge.Its a latch the value of Q is when clock is changing on the rising edge,so Q is written only when clock is with positive logic,as I can see Y changes with the falling edge on the second rising egde of C so probably is Y for negative logic?
By definition, a latch is not clocked; the inputs are level sensitive. If you cascade two latches, you can have an edge (master slave) triggered flip flop. That's why I need more information on how the flip flops are constructed.Just see the truth table about SR latch
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by Ikimi .O