I just learned about mosfets in buck converter today. The output voltage is supposed to be determined by the duty cycle of the signal at the mosfet gate.

So, I had tried simulation but somehow i do not understand why rather than the output voltage depends on the duty cycle, it depends more on the amplitude of the signal applied at the gate . Why is that ?

 

Hi, I am new here. I don't have an answer to your question, but can I ask you what program that is you are using?

 

Hi .. The program i used is multisim v11

 

Without answering your original question, let me point out a few things.
You have no load, so the cap gets a continual kick of current - as current goes in voltage goes up, integrator.
There is no feedback to turn off the pulse train once the voltage is achieved. This is not necessary if the load and the PWM duty are balanced, but without a load that cap will eventually reach 12 v.
Put the scope on your gate, look a the drive, I'm not familiar with that program, so if the square wave is +2.5 to -2.5, you are barely reaching the threshold of the FET to turn on. Make sure the parameters are such that the gate is switching between 5v and 0.
Once you have addressed these points you might see a difference.
You should scope the voltage across your R1 resistor, you should see a saw tooth pattern.

 

The IRF530 is a standard-level N-ch enhanced MOSFET.
Look at the datasheet. Rds(on) is specified when Vgs=10v (voltage on the gate, referenced to the source terminal). This means that in order to turn the mosfet fully ON, you must get Vgs to 10v.

However, you have the PWM source referenced to ground, rather than the source terminal. This means that the output voltage will never stay higher than the PWM peak output voltage on the gate, less the threshold of the MOSFET.

You need a load on the output.

R1 doesn't serve much of a purpose except it limits the maximum output current to 6A if the output is shorted.

 

On the output load ; so if i put a resistor ,say, 1 ohm i will get 6V ?

On the Vgs ; does that mean i have to measure voltage between gate and source and increase the gate voltage until it reaches 10V between gate and source ? Or does it mean i have to connect the -ve terminal of the signal generator to the source for proper reading on Vgs ?

 

You really should read up some on the design of SMPS.
Here's a good link for you: http://www.smps.us/smpsdesign.html

 

Without answering your original question, let me point out a few things.
You have no load, so the cap gets a continual kick of current - as current goes in voltage goes up, integrator.
There is no feedback to turn off the pulse train once the voltage is achieved. This is not necessary if the load and the PWM duty are balanced, but without a load that cap will eventually reach 12 v.

How to build a feedback with common electronics components ?