Hi,
Can anyone help me explain why we have the state reset =0, q(n) = 0, q(n+1)=0 in the below picture?

 

Nope. It seems to me that you have contradictory entries in the table (the middle line and the last line).

Where did you get the table from? If possible, ask your instructor what it is supposed to mean.

 

Nope. It seems to me that you have contradictory entries in the table (the middle line and the last line).

Where did you get the table from? If possible, ask your instructor what it is supposed to mean.

It is a example in Verilog HDL: A Guide to Digital Design and Synthesis by Samir palnitkar.

 

I don't know if I have that particular text or not. But without looking at the entire context in which the table is given, my impression is that it is a mistake in which the author copied a table from earlier in the book and modified it but didn't delete that row.

 

I agree with WBahn. It can get pretty frustrating when you read a badly revised edition of a textbook.