I have started playing with an AD9834 sythesizer which has a variable reference clock ( 50 MHZ ocxo on board). The synthesizer comes with some basic software to start you off, you can set up two frequency registers and two phase register and you can also adjust the reference clock. I will come to the point when I reduce the reference clock frequency by a factor of five the output frequency of the DDS is actually multiplied by the same factor.

Reference clock 50MHz output 1MHz
change reference to 10MHz the output changes to 5 MHz ???!!!

I would have expected the output to be reduced ( f = phasexMCLK/2pi)

If you reduce the multiplier doesn't it reduce f?? Can anybody through any light on what I think I am seeing

 

I dunno, but if you follow that logic to the extreme, you should be able to lower the clock to 1Hz and get blue light at the output!

 

Originally posted by Ron H@Mar 8 2006, 11:03 PM
I dunno, but if you follow that logic to the extreme, you should be able to lower the clock to 1Hz and get blue light at the output!

[post=14787]Quoted post[/post]​

What are you trying to say?

 

Originally posted by ChatMember@Mar 8 2006, 06:50 PM
What are you trying to say?

[post=14789]Quoted post[/post]​

That the frequency of Blue Light is in the neighborhood of 475 TeraHertz. Basically it's a wiseacre comment, meant to be funny, about your hypothesis and assumptions. All sorts of false conclusions can be logically deduced from them.

More helpful would be to suggest a complete review of everything that you know about the circuit and the datasheet. Did this chip come on an evaluation board, or are you hooking it up yourself? I would look for pins which need to be tied or jumpered somwhere and are not. Maybe they go somewhere but not to the correct place. In short one or more of your assumptions is leading you astray.

 

Originally posted by ChatMember@Mar 8 2006, 04:54 PM
I have started playing with an AD9834 sythesizer which has a variable reference clock ( 50 MHZ ocxo on board). The synthesizer comes with some basic software to start you off, you can set up two frequency registers and two phase register and you can also adjust the reference clock. I will come to the point when I reduce the reference clock frequency by a factor of five the output frequency of the DDS is actually multiplied by the same factor.

Reference clock 50MHz output 1MHz
change reference to 10MHz the output changes to 5 MHz ???!!!

I would have expected the output to be reduced ( f = phasexMCLK/2pi)

If you reduce the multiplier doesn't it reduce f?? Can anybody through any light on what I think I am seeing

[post=14786]Quoted post[/post]​

I don't know this synthesizer but here is what I think. In a synthesizer there is a reference frequency, an output frequency, and an feedback frequency. The reference is usually constant. The output is a multiple of the reference that gets divided digitally to match the reference. A phase locked loop forces the feedback frequency to match the reference frequency. This way you can get an exact multiple of the reference. As and equation;

Fo = Fref * n Ffb = Fo/n

I'm guessing your highest freqency, 50MHz, is really an output and the lowest, 1 MHz, is really the feedback, and you have another reference. When you change the divider, the output went to 10Mhz and because you reduced your divider by a factor of 5. This will cause the feedback frequency to increase by a factor of 5. The reference should be constant. In some synthesizers there is another divider between the refrence and the PLL. This changes the equation to;

Fo = Fref * n/m Ffb = Fo/n

There isn't really a reason to use a synthesizer to go from 50MHz to 1MHz because dividing can be done more simply. I hope this helps.

 

Originally posted by aac@Mar 9 2006, 02:39 PM
I don't know this synthesizer but here is what I think. In a synthesizer there is a reference frequency, an output frequency, and an feedback frequency. The reference is usually constant. The output is a multiple of the reference that gets divided digitally to match the reference. A phase locked loop forces the feedback frequency to match the reference frequency. This way you can get an exact multiple of the reference. As and equation;

Fo = Fref * n Ffb = Fo/n

I'm guessing your highest freqency, 50MHz, is really an output and the lowest, 1 MHz, is really the feedback, and you have another reference. When you change the divider, the output went to 10Mhz and because you reduced your divider by a factor of 5. This will cause the feedback frequency to increase by a factor of 5. The reference should be constant. In some synthesizers there is another divider between the refrence and the PLL. This changes the equation to;

Fo = Fref * n/m Ffb = Fo/n

There isn't really a reason to use a synthesizer to go from 50MHz to 1MHz because dividing can be done more simply. I hope this helps.

[post=14811]Quoted post[/post]​

The reason I am using a direct synthesis from 50 Mhz is to allow me to be able to switch to any frequency below that frequency. Using an oven controlled stable source.
Reading the data sheet there is a possibility that the harmonics from the reference oscillator 50Mhz is getting on the the output frequency of 1 MHz, as the reference frequency is brought closer to the output frequency the harmonics can slip under the skirts of the filter, also as the reference frequency is reduced the number of phase samples used from the phase register is also reduced therefore producing more quantisation error/ time discatisation noise! (Harmonics) close to output signal?
There is a lot going on!