Hello
Can someone advise how to implement delays in Verilog?
I've tried googling it and it either takes me to test benches or to some advanced papers which I don't understand.
Do I have to implement some sort of "request -> counter -> permission" sort of thing to get a proper delay?
Can someone advise how to implement delays in Verilog?
I've tried googling it and it either takes me to test benches or to some advanced papers which I don't understand.
Do I have to implement some sort of "request -> counter -> permission" sort of thing to get a proper delay?