This is a small block of my project. I need design a 7-bit counter which clocks rising edges of signal fvco(range: 4Mhz to 100Mhz,variable). A reference frequency fref =1Mhz asynchronous reset the counter at the rising edge of fref signal(it reset the counter output to 0 very 1us). Just prior to asynchronous reset, the counter give output.

It is simple to write a verilog code with two always @(posedge fref) and always@(posedge fvco). But this kind of code can't be synthesis.

Please help to write a synthesisable verilog code.

Thanks a lot

 

Complementary description for frequency counter:
The counter need count how many fvco(frequency variable) rising edge arrived during 1us time interval. Sample the counter at the rising edge of fref(1M hz) then reset the counter, continue to count for next 1us time. Thus we can get the frequency of fvco during every 1us time interval.

The code like this does not work:

always @ (posedge fref or posedge fvco)
begin
if(fref)
begin
counter<=0;
cuonter_output<=counter;
end
else
counter<=counter+1;
end

It doesn't work because when fref=1 (duration for 500ns), the counter will be reset to 0 and do not count the rising edge of fvco.

Can anyone give me any suggestion?