Is this syntax mistaken; thanks for help.
What I want to do is to slice _ii_pp_qq_kk into ii, pp, qq, kk and pp_qq. That way I reference a specific slice as a name.
ENTITY Kcn_entity IS
PORT
(
-- -- -- clk : std_logic ; -- The Clock
-- -- -- ii.pp.qq.kk, with kk = "01"
-- -- -- out_bits_ii_pp_qq_kk : OUT std_logic_vector ( 7 DOWNTO 0) ;
-- ab.cd.ef.gh as ii.pp.qq.kk
inp_bits_ii_pp_qq_kk : IN std_logic_vector ( 7 DOWNTO 0) ;
inp_bits_ii : IN TYPE inp_bits_ii_pp_qq_kk ( 7 DOWNTO 6) ; -- ii
inp_bits_pp : IN TYPE inp_bits_ii_pp_qq_kk ( 5 DOWNTO 4) ; -- pp
inp_bits_qq : IN TYPE inp_bits_ii_pp_qq_kk ( 3 DOWNTO 2) ; -- qq
inp_bits_kk : IN TYPE inp_bits_ii_pp_qq_kk ( 1 DOWNTO 0) ; -- kk
inp_bits_pp_qq : IN TYPE inp_bits_ii_pp_qq_kk ( 5 DOWNTO 2) ; -- pp_qq
) ;
END Kcn_entity ;
What I want to do is to slice _ii_pp_qq_kk into ii, pp, qq, kk and pp_qq. That way I reference a specific slice as a name.
ENTITY Kcn_entity IS
PORT
(
-- -- -- clk : std_logic ; -- The Clock
-- -- -- ii.pp.qq.kk, with kk = "01"
-- -- -- out_bits_ii_pp_qq_kk : OUT std_logic_vector ( 7 DOWNTO 0) ;
-- ab.cd.ef.gh as ii.pp.qq.kk
inp_bits_ii_pp_qq_kk : IN std_logic_vector ( 7 DOWNTO 0) ;
inp_bits_ii : IN TYPE inp_bits_ii_pp_qq_kk ( 7 DOWNTO 6) ; -- ii
inp_bits_pp : IN TYPE inp_bits_ii_pp_qq_kk ( 5 DOWNTO 4) ; -- pp
inp_bits_qq : IN TYPE inp_bits_ii_pp_qq_kk ( 3 DOWNTO 2) ; -- qq
inp_bits_kk : IN TYPE inp_bits_ii_pp_qq_kk ( 1 DOWNTO 0) ; -- kk
inp_bits_pp_qq : IN TYPE inp_bits_ii_pp_qq_kk ( 5 DOWNTO 2) ; -- pp_qq
) ;
END Kcn_entity ;