synchronous counter problem

Discussion in 'Homework Help' started by deadlyamplifier, Nov 25, 2009.

  1. deadlyamplifier

    Thread Starter New Member

    Oct 10, 2009
    i have been asked to design a synchronous counter which counts in the following sequence 0,3,6,9,12,15,0.........can anyone help me out?
  2. ATM


    Oct 8, 2009
    Have you attempted anything so far? I know how to do it but I don't just want to give you the answer, it's so much more rewarding when you achieve it yourself. :)

    Heres a hint though; I would use an adder with a 'Cin' of 3. And if you use a four-bit bus, the maximum value you can have is 1111 which is 15.

    If you're still completely stuck, let me know.
  3. deadlyamplifier

    Thread Starter New Member

    Oct 10, 2009
    .hmm i get what u mean let me tell u what i have done till now......i started by considering the present and next states of the data and then i made a table with the excitation table of a t flip flop.......i know i have to use four flip flops and then get logic from k maps and then implement using gates but i need to be sure about my answer........m preparing for my do reply......
  4. Papabravo


    Feb 24, 2006
    If I were you I'd forget about the T-flipflop since the only thing it can do on each clock edge is toggle. A D-flipflop will at least accept a value of `0' or `1' on each clock edge. From the Karnaugh maps it should be obvious weather it is better to implemnt the `1's or the `0's.

    Moving head and shoulders over your competition, consider the JK flipflop which can do four different things on each clock edge. It can toggle, hold, set, and clear.