HI all,
I need help in understanding synchronous active low reset in D-flipflops. As I get it,state of the flipflop is dependent on clock cycle(synchronous) and rising clock edge(active) but what is low here? reset is resetting the flipflop to zero. If we have to draw this D-flip with transmission gates(4), does this schematic include a two input AND gate(D, reset) or (d, reset_n) before the transmission gate?
Thanks,
Sara.
I need help in understanding synchronous active low reset in D-flipflops. As I get it,state of the flipflop is dependent on clock cycle(synchronous) and rising clock edge(active) but what is low here? reset is resetting the flipflop to zero. If we have to draw this D-flip with transmission gates(4), does this schematic include a two input AND gate(D, reset) or (d, reset_n) before the transmission gate?
Thanks,
Sara.