# Switch

#### menewbie

Joined Jan 31, 2006
34
Hi, does anyone know how to design a switch so that it passes both positive and negative voltage?
If I use NMOS switch or the CMOS transmission gate, the lowest voltage can be passed is -Vthn, which is the threshold voltage for NMOS. So far, I know the PMOS switch would work. But the switch I am trying to design has to connect to one of the two power supplies. So, if the PMOS switch connects to the negative power supply, then it can pass the negative voltage. However, when it connects to the positive power supply, it doesnt pass the positive voltage.

I have attached a file that shows the switch that I am suppose to design. The positive power supply is Vref and the negative power supply is -Vin.

#### Papabravo

Joined Feb 24, 2006
14,883
Originally posted by menewbie@Mar 2 2006, 01:05 AM
Hi, does anyone know how to design a switch so that it passes both positive and negative voltage?
If I use NMOS switch or the CMOS transmission gate, the lowest voltage can be passed is -Vthn, which is the threshold voltage for NMOS. So far, I know the PMOS switch would work. But the switch I am trying to design has to connect to one of the two power supplies. So, if the PMOS switch connects to the negative power supply, then it can pass the negative voltage. However, when it connects to the positive power supply, it doesnt pass the positive voltage.

I have attached a file that shows the switch that I am suppose to design. The positive power supply is Vref and the negative power supply is -Vin.
[post=14528]Quoted post[/post]​
Is this a board level design or a chip level design?
What does the control voltage for the switch look like?
What does the S/H mean inside the block connected to -Vin ?

#### menewbie

Joined Jan 31, 2006
34
Originally posted by Papabravo@Mar 2 2006, 06:01 PM
Is this a board level design or a chip level design?
What does the control voltage for the switch look like?
What does the S/H mean inside the block connected to -Vin ?
[post=14533]Quoted post[/post]​
This is a transistor level desing.
The control voltage for the switch is either high (5V) or low (0V). It really depends on the switch. For example, if it's PMOS switch, which requires negative voltage to turn it on, then the control voltage would be different.
S/H is sample and hold amplifier.

#### n9352527

Joined Oct 14, 2005
1,198
It's just impossible. Vdd and Vss of any combination of NMOS and PMOS gate have to be respectively higher and lower than any input voltage (signal) that the gate processes. Otherwise it'd be operating outside its designed region. i.e. No signal higher than PMOS substrate voltage and no signal lower than NMOS substrate voltage.

What you observed (-Vth) was the residual charge that the switch couldn't dissipate due to not enough Vgs.

You need a transmission gate, with appropriate Vdd and Vss.

#### menewbie

Joined Jan 31, 2006
34
Hi n9352527, thank you for the reply. I have considered the transmission gate. I have attached a diagram of it to this reply. What I dont know is where do I apply Vdd and Vss. In the diagram shown, A is connected to either one of the power supplies. B is connected to the another terminal. (In my design, B is connected to the input of the integrator. CK represents the compliment of the clock signal. The clock signal is either high (5V) or low (0V).

So, from the diagram where do I connect the appropriate Vdd and Vss to?
May I use Vdd as the clock signal and use Vss as the compliment of the clock signal?

If I may, then how do I turn off the transmission gate? I turn off the transmission gate by switching the two signals? i.e. apply Vdd to the gate of PMOS and apply Vss to the gate of NMOS. To turn it on, apply Vdd to the gate of NMOS and apply Vss to the gate of PMOS. If that is the case, then how do I generate Vss. Vdd is about 5V. I can generate that by using a digital voltage buffer. But Vss has to be
-5V...and I am not so sure how can I generate that signal. I am very confused...

Please enlarge the attached diagram so that it is more clear.

#### pebe

Joined Oct 11, 2004
626
Originally posted by menewbie@Mar 2 2006, 10:04 AM
Hi n9352527, thank you for the reply. I have considered the transmission gate. I have attached a diagram of it to this reply. What I dont know is where do I apply Vdd and Vss. In the diagram shown, A is connected to either one of the power supplies. B is connected to the another terminal. (In my design, B is connected to the input of the integrator. CK represents the compliment of the clock signal. The clock signal is either high (5V) or low (0V).

So, from the diagram where do I connect the appropriate Vdd and Vss to?
May I use Vdd as the clock signal and use Vss as the compliment of the clock signal?

If I may, then how do I turn off the transmission gate? I turn off the transmission gate by switching the two signals? i.e. apply Vdd to the gate of PMOS and apply Vss to the gate of NMOS. To turn it on, apply Vdd to the gate of NMOS and apply Vss to the gate of PMOS. If that is the case, then how do I generate Vss. Vdd is about 5V. I can generate that by using a digital voltage buffer. But Vss has to be
-5V...and I am not so sure how can I generate that signal. I am very confused...

Please enlarge the attached diagram so that it is more clear.
[post=14539]Quoted post[/post]​
I'm not quite clear about your voltages. Is Vref=5V and -Vin=0V?
If so use two sections of a 4016 or 4066 with Vdd=5v and Vss=0v. CK to control one, and CK to control the other so only one switches at a time.

The RCA data on the chip says it will pass through all signals whose levels lie between Vdd and Vss.

#### Papabravo

Joined Feb 24, 2006
14,883
Originally posted by pebe@Mar 2 2006, 03:58 PM
I'm not quite clear about your voltages. Is Vref=5V and -Vin=0V?
If so use two sections of a 4016 or 4066 with Vdd=5v and Vss=0v. CK to control one, and CK to control the other so only one switches at a time.

The RCA data on the chip says it will pass through all signals whose levels lie between Vdd and Vss.
[post=14546]Quoted post[/post]​
A DG419 can have dual supplies and pass any voltage between V+ and V-
So connect -Vin to the V- pin and one of the inputs. Connect Vref to V+ and the other input. The output will be the common terminal. Use your logic signal to select one input or the other or the other and be done with it.

For the life of me I cannot figure out what the Sample and Hold Amplifier is there for. Can you explain this?

#### n9352527

Joined Oct 14, 2005
1,198
Vdd should be connected to the PMOS substrate. Vss should be connected to NMOS substrate.

You should modify your control voltage so that it swings between Vdd and Vss (NOT Vdd and 0V). PMOS and NMOS gates are driven by complementary signal (Vdd on NMOS gate and Vss on PMOS gate would turn the switch on, Vss on NMOS gate and Vdd on PMOS gate would turn the switch off).

With this configuration, you would be able to switch input signal in the range of Vdd to Vss, no more and no less. So if you have an input signal in the range of +5V to -5V, you would need Vdd >= +5V and Vss <= -5V.

You would need to provide external Vdd and Vss supply to the circuit. They are not generated internally, unless you want to go through the pain of designing a charge pump too.

#### windoze killa

Joined Feb 23, 2006
605
To generate to -5V that would make this easier you can use a TI PT5022. This is a module that produces -5V from a 5V supply. I have used these extensively and they work very well. They are also available in other voltages.

#### n9352527

Joined Oct 14, 2005
1,198
He is designing a chip level circuit, at least that was what I gathered from his posts. The S/H is intended for an ADC front-end. So using any external component or IC is not really a preferable solution.

#### Papabravo

Joined Feb 24, 2006
14,883
Originally posted by n9352527@Mar 3 2006, 01:26 PM
He is designing a chip level circuit, at least that was what I gathered from his posts. The S/H is intended for an ADC front-end. So using any external component or IC is not really a preferable solution.
[post=14576]Quoted post[/post]​
I guess when I asked if he was doing a chip level design or a board level design and he answered that it was a "transistor level design" I figured he meant "transistors on a board". That is why I suggested the DG419: I'm sorry for my confusion.

#### windoze killa

Joined Feb 23, 2006
605
Originally posted by Papabravo@Mar 4 2006, 09:08 AM
I guess when I asked if he was doing a chip level design or a board level design and he answered that it was a "transistor level design" I figured he meant "transistors on a board".  That is why I suggested the DG419: I'm sorry for my confusion.
[post=14590]Quoted post[/post]​
And thats why I suggested the external -5V regulator module also. Where did he say it was an internal chip design?

#### pebe

Joined Oct 11, 2004
626
Originally posted by windoze killa@Mar 3 2006, 10:33 PM
And thats why I suggested the external -5V regulator module also. Where did he say it was an internal chip design?
[post=14594]Quoted post[/post]​
Perhaps 'menewbie' could clarify just what type of device he wants to use. Discretes or ICs?

#### menewbie

Joined Jan 31, 2006
34
Originally posted by n9352527@Mar 3 2006, 09:44 PM
Vdd should be connected to the PMOS substrate. Vss should be connected to NMOS substrate.

You should modify your control voltage so that it swings between Vdd and Vss (NOT Vdd and 0V). PMOS and NMOS gates are driven by complementary signal (Vdd on NMOS gate and Vss on PMOS gate would turn the switch on, Vss on NMOS gate and Vdd on PMOS gate would turn the switch off).

With this configuration, you would be able to switch input signal in the range of Vdd to Vss, no more and no less. So if you have an input signal in the range of +5V to -5V, you would need Vdd >= +5V and Vss <= -5V.

You would need to provide external Vdd and Vss supply to the circuit. They are not generated internally, unless you want to go through the pain of designing a charge pump too.
[post=14566]Quoted post[/post]​
This is very very helpful. Thank you very much, I think I know how to design the switch.

#### menewbie

Joined Jan 31, 2006
34
Originally posted by windoze killa@Mar 4 2006, 10:33 AM
And thats why I suggested the external -5V regulator module also. Where did he say it was an internal chip design?
[post=14594]Quoted post[/post]​
n9352527 is right. I am designing a chip level circuit. Sorry that I have caused some confusion.

#### windoze killa

Joined Feb 23, 2006
605
Originally posted by menewbie@Mar 4 2006, 06:22 PM
n9352527 is right. I am designing a chip level circuit. Sorry that I have caused some confusion.
[post=14634]Quoted post[/post]​
I wouldn't mind a little bit of clarification still. Are you designing a circuit using chips or are you designing the internal workings of a chip?

#### menewbie

Joined Jan 31, 2006
34
Originally posted by windoze killa@Mar 4 2006, 09:32 PM
I wouldn't mind a little bit of clarification still. Are you designing a circuit using chips or are you designing the internal workings of a chip?
[post=14636]Quoted post[/post]​
I am designing the internal workings of a chip.

#### windoze killa

Joined Feb 23, 2006
605
Originally posted by menewbie@Mar 4 2006, 10:25 PM
I am designing the internal workings of a chip.
[post=14639]Quoted post[/post]​
Thanks. That explains it a bit more.