Successive approximation ADC doubt!

Discussion in 'General Electronics Chat' started by sndpgr, Apr 11, 2008.

  1. sndpgr

    Thread Starter Member

    Jun 22, 2006

    I am trying to figure out how it works. here are what I have understood..

    - the counter sequence is 1000 1100 1110 1111(assuming 4 bit conversion).

    -1st the output of counter is 1000 this is converted to its analog(by D/A) and
    compared to the input by the comparator. where is the output of the comparator connected to the SAR?

    -The inputs to the DAC are connected to SRG ,what is that?

    How does the circuit know when the conversion is done??
    Hope you understood my queston!!
  2. bertus


    Apr 5, 2008
  3. Norfindel

    AAC Fanatic!

    Mar 6, 2008
    I was into something like this once. The idea is that to get the digital value, you use a special counter, a DAC, and an analog comparator. The idea is to set the MSB to high and sense if the value generated by the DAC is bigger or smaller than the analog signal you're measuring. If it's smaller, you set that bit to 0, and go to the next bit. If it's larger, you keep that bit at 1, and go to the next bit. When you finally arrive to the LSB, the output of the DAC is as close as the analog signal as this can be. Probably that SRG is just a latch, that keeps the binary value while the DAC is working on another conversion. Never seen a latch "labeled" as SRG, but seems to be the logical option there.