Hey guys,

I'm trying to create a 4bit locking mechanism and I've got like a counter mechanism that says to which bit number, data must be stored.

I.e.: 1st I want to save data to first bit either 1 or 0, depending on the input. Then I want to save data to 2nd bit, 3rd and 4th bit. Each bit should be saved to it's own component.

And once I get all 4 bits settled I will send them to another component which unlock or lock the device. But that's not really important.

My question is, how do I store bit data to a component? I'm currently using Xilinx. Cheers

Attempt: I thought that if I make a double NOT gate component and circle the bit around, but there's probably a better way to do it?

 

The component you use to store 1 bit of data is a flip-flop or a latch. A flip-flop stores 1-bit of data, present at its input(s), on the rising or falling edge of a clock signal. A latch, on the other hand, passes the input to the output (is transparent) when it is enabled. It holds the data that is present at the input on the trailing edge of the enable signal.

Synthesizing a latch from gates is straightforward. It is usually done as a sum of 3 product terms. Doing a flip-flop, from gates, is also possible but why bother when the FPGA gives you an optimized function block.

 

I'm a bit confused by your explanation, however, it sounds like you want a sequence detector - a typical application for learning finite state machines (FSMs).

 

I'm a bit confused by your explanation, however, it sounds like you want a sequence detector - a typical application for learning finite state machines (FSMs).

My explanation or the OPs problem statement?

 

My explanation or the OPs problem statement?

The problem statement. Your response wasn't there when I wrote my response.

 

The component you use to store 1 bit of data is a flip-flop or a latch. A flip-flop stores 1-bit of data, present at its input(s), on the rising or falling edge of a clock signal. A latch, on the other hand, passes the input to the output (is transparent) when it is enabled. It holds the data that is present at the input on the trailing edge of the enable signal.

Synthesizing a latch from gates is straightforward. It is usually done as a sum of 3 product terms. Doing a flip-flop, from gates, is also possible but why bother when the FPGA gives you an optimized function block.

Ok, so I've found 2 different flip-flops:

and they are 2 different components. I couldn't really find anything useful on these components but can you tell me which one is better?

Cheers

 

I didn't know the difference until just a few minutes ago. An IFD is contained within an input block. I'll bet an OFD is contained in an output block. Neither of these is necessarily what you want.

http://www.cs.indiana.edu/hmg/le/pr...c/usenglish/de/libs/spartan3e_sch/ifd4816.pdf

http://www.cs.indiana.edu/hmg/le/pr...doc/usenglish/de/libs/spartan3e_sch/ofd_1.pdf

You need to dig deeper and read more carefully. This is not something you can do by the seat of your pants.

How about this:
http://www.cs.indiana.edu/hmg/le/pr...doc/usenglish/de/libs/spartan3e_sch/ofd_1.pdf

or this
http://www.cs.indiana.edu/hmg/le/pr....1/doc/usenglish/de/libs/spartan3e_sch/ld.pdf

Hint: after following one of these links, backspace over the .pdf file name to the slash and hit return to pull up a directory of parts and browse to your hearts content.

 

Thanks for the info. I'll stick with LDC because it's all the required functionality and a clear button, which is essential. Also, thanks on showing the library, that's gonna help me a lot in the near future. Cheers

 

Thanks for the info. I'll stick with LDC because it's all the required functionality and a clear button, which is essential. Also, thanks on showing the library, that's gonna help me a lot in the near future. Cheers

Just to be clear, that library is for a Spartan 3e chip and is dated 2005. Is that what you are using?

 

Just to be clear, that library is for a Spartan 3e chip and is dated 2005. Is that what you are using?

I'm currently using Virtex5. In that same library Virtex4 is available. I tried searching for Virtex5 in ISE 13.2 (My current version is 14.2) but didn't quit found the documentation for it. I should be able to find it later on.

Cheers

 

Virtex5 guide

http://www.xilinx.com/support/documentation/sw_manuals/xilinx11/virtex5_hdl.pdf
http://www.xilinx.com/itp/xilinx10/books/docs/virtex5_scm/virtex5_scm.pdf

Tell me again why you can't you find this stuff?

It takes about 30 seconds to do a ggogle search.

 

Hey guys,

I'm trying to create a 4bit locking mechanism and I've got like a counter mechanism that says to which bit number, data must be stored.

I.e.: 1st I want to save data to first bit either 1 or 0, depending on the input. Then I want to save data to 2nd bit, 3rd and 4th bit. Each bit should be saved to it's own component.

And once I get all 4 bits settled I will send them to another component which unlock or lock the device. But that's not really important.

My question is, how do I store bit data to a component? I'm currently using Xilinx. Cheers

Attempt: I thought that if I make a double NOT gate component and circle the bit around, but there's probably a better way to do it?

You do NOT want to make circuits such as inverters circling back around on themselves (i.e., fundamental mode feedback sequential circuits) in an FPGA. FPGA's almost universally implement combinatorial logic via RAM-based look up tables (LUTs) and those are very glitchy and very sentitive to glitches. But you also have LOTS of registers in an FPGA. USE THEM!

 

Ok, so I've found 2 different flip-flops:

and they are 2 different components. I couldn't really find anything useful on these components but can you tell me which one is better?

Cheers

Be sure that you ONLY use proper clock signals into the clock inputs on any part you use. Preferably just one clock signal that goes to every clock input in your design. If you start using logic to generate signals to clock your flip flops, you are asking for (and will almost certainly receive in very short order) lots of trouble. Never use gated-clocks in an FPGA-based design. Been there. Done that. Trust me -- you do NOT want that particular tee shirt!