Static ram

Thread Starter

mentaaal

Joined Oct 17, 2005
451
Hey guys,

Quick question in relation to static ram. In my notes, it says that "no harm is done by changing the address lines while the o/p bus is enabled."
What is meant here is, if the values on the address bus is changed while the output is enabled (during a read operation) it is ok.
I am just wanting to know why this is the case? When the output is enabled, do the outputs going to the address bus not change? is it not important for this to change only at certain times to ensure that the right device gets the right information?

Thanks,
Greg

 

hgmjr

Joined Jan 28, 2005
9,029
There is no harm to the memory device if you change the state of the address lines with the data output line enabled for read.

There may be adverse impact on the data itself since there is the potential for a collision between the data output lines and some other devices that is attached to the data-bus.

hgmjr
 

Thread Starter

mentaaal

Joined Oct 17, 2005
451
perfect thanks for that. Yeah thats what i was thinking, so there has to be some logic in the system to ensure that the addresses are not changed during a read operation.

Isnt there a possibility that the information put on the bus when the address input is changing may be undefined because, as the SRAM sells are essentially asynchronous circuits?
 

hgmjr

Joined Jan 28, 2005
9,029
perfect thanks for that. Yeah thats what i was thinking, so there has to be some logic in the system to ensure that the addresses are not changed during a read operation.

Isnt there a possibility that the information put on the bus when the address input is changing may be undefined because, as the SRAM sells are essentially asynchronous circuits?
Indeed, if the timing restraints that are defined for a read operation are not followed with care there is a strong likelihood that not only data but also there is a possibility that program execution will be adversely impacted in those cases were data and program instructions are fetch over a common data bus.

hgmjr
 
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