Stacking BJT Switches?

Thread Starter

liquidair

Joined Oct 1, 2009
192
Hi all-

I am designing a fairly complicated switching circuit where I need the functionality of an AND gate but am not too keen on using them. I am using mom pushbuttons to control CMOS logic. The logic outputs will drive a darlington (so as not to draw so much current) which will switch a relay bank. There are some instances where I need "relay a" to switch if "bank a" is on and that option is called, and "relay b" if "bank b" is on, etc.

AND gates would do this but another much simpler way of doing this would be to stack my driver transistors (which I would need anyhow, with or without the AND gate) one on top of each other. Using the above example, the bottom BJT would turn the relay bank on or off and the top bjt would control the optional relays. This way both transistors need to be on for the option to turn on.

Is there any problems or considerations to do this? Any easier way?

Thanks in advance!
 

SgtWookie

Joined Jul 17, 2007
22,230
A problem could be the Darlington Vce. Depending on Ic, the Vce might be anywhere from ~0.7v to 1.6v. If you have stacked Darlingtons, that Vce will be cumulative, and could very quickly prevent the relays from energizing.

Relays usually need ~70% of their rated voltage in order to engage. If, for instance, you're dealing with 12v relays, 70% of 12v is 8.4v; 12-8.4v = 3.6v, and half of that is 1.8v. That's getting rather close to the 1.6v that a Darlington might drop in Vce under load; so you would have to check the specs carefully to ensure that it will be guaranteed to work.
 

Thread Starter

liquidair

Joined Oct 1, 2009
192
I realized that might have been an issue but seeing the math makes me want to relook at other possiblities. The obvious way to counter that would be to raise the supply voltage a bit, but then you use up more energy in the coil. Another concern I have is that the higher level relay group "ground" would need to be connected between the T2 emitter and T1 collector. When T1 (the transistor connected directly to ground) is off, then the voltage appearing at the E-C junction would be the full supply voltage which could exceed T2's Vbe rating.

Is there another way to get AND functionality using transistors using CMOS logic outputs as our control signals? The reason I'm opposed to just using ANDs and being done with it is the size of the ICs and to avoid having a huge number of bus traces. We get around this if we place the ANDs near the switch itself but there's not space.
 

SgtWookie

Joined Jul 17, 2007
22,230
Rather than Darlingtons, you could use small general-purpose NPN's as voltage followers to source more current to a standard BJT. Stack these smaller general-purpose NPNs and let the emitter drive the bases.
[eta]
Use a single resistor on the emitter of the lowest voltage follower in the stack to limit base currents for all of the transistors.
[eta]
whoops, the single emitter resistor won't work so well. Time to re-think that.
 
Last edited:

SgtWookie

Joined Jul 17, 2007
22,230
Rather than using BJTs or Darlingtons, why not use logic-level N-ch MOSFETs? Just use a Zener from the source to the gate to make sure that the ±Vgs limit is not exceeded.
 

Thread Starter

liquidair

Joined Oct 1, 2009
192
I originally was planning on using MOSFETs as I really like them in power supplies. However, there was my hang up. I normally use them as followers so I am used to the Vgs coming into play and pulling the output down by that amount. I assumed that would happen as well here, so I figured we'd be dropping 2-3V across each MOSFET, in which case the darlington wins. Simulations are showing drops in the mV, so I think we have a winner! Since I'm using 4000 series logic at 12-15V, do I even need a LL MOSFET or can I just use whatever is convienient? Thanks for your help on this!
 

SgtWookie

Joined Jul 17, 2007
22,230
Since you have >10v available, you can likely use whatever MOSFET is handy. I'd suggest using a resistor between the 4000 series output and the MOSFET gate though; that will keep the gate from "ringing" when the state of the output is changed. It will also reduce peak loads on the IC.
 
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