hi
plz help me in this problem
use four 8-bit SRSL (shift Register serial LEFT )registers with load new value capability to design an up counter which produces even numbers between 0 to F hex .
use any other logic components you find them necessary for the design
to be even the LSB must be zero right ?
do i need a mux here !!?
plz help me in this problem
use four 8-bit SRSL (shift Register serial LEFT )registers with load new value capability to design an up counter which produces even numbers between 0 to F hex .
use any other logic components you find them necessary for the design
to be even the LSB must be zero right ?
do i need a mux here !!?
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