So knowing what an SR latch looks like.

Im failing to understand one thing, and thats the initial state of Q/Qnot.

I understand how the SR latches work, but how do we get the first Q value (Or gate output values). Like pretend the computer is first turning on.....

Like We send a 1 to R....but the input below R (on the same gate) depends on the Output of the S latch, and we send a 0 to S....but the input right next to S (On the same gate) relies on the output of the R gate......So were stuck in no mans land since neither of the gates have an output yet?

Like even going more basic, a NOR gate with 2 zero inputs would have an output of 1.....but would this be true if it was FIRST turned on (Since no signal would've even been applied?)

does that make sense?

 

It is indeterminable. The output will usually, be stuck in what's called the metastable state, neither 1, or 0 for some time. It will eventually resolve itself into one state due to slight variations in the implementation, or the inputs force the state....

For the combinational logic gate, the output does not reflect the input until what is referred to as the propagation delay, the time it takes for the output to respond to the corresponding inputs.

 

The indeterminate state at startup is why many digital systems use a Power On Reset (POR) to set the system to a known state when power is applied.

 

OK well have can an output even happen? Since both Gates require feedback from an Output state of the gate (Which we don't have yet since.....it had just been turned on). Or can we get an Output from each gate with just 1 input line coming in (Since the "feedback" inputs won't have any value yet)

 

As the power comes up the outputs will tend to go up (since the inputs start out low also). Due to inherent imbalances in the circuit (since it's not perfect) one will come up slightly faster than the other. When it gets high enough it will turn on the connected gate, which will then turn off the cross coupled output. So it will always come up in a state with one output high and the other low. You just won't know which one it will be (unless you're clairvoyant).

 

So even with 1 (low) input on each gate, the output can still be High (basically what im asking is that if you only have 1 low input, can it still change the gate if the other input on the gate isn't determined yet (the one that is the feedback input line)

 

It is a NOR gate so when both inputs are low, the output is high. The first output to reach the logic threshold of the cross-coupled gate, will force that output low, thus determining the initial state of the circuit.

 

So even with 1 (low) input on each gate, the output can still be High (basically what im asking is that if you only have 1 low input, can it still change the gate if the other input on the gate isn't determined yet (the one that is the feedback input line)

I think you are misunderstand what is meant by indeterminate. The state that is presented on the outputs of a gate, before the propagation delay is reached, is still a valid input, though it may, or may not, lie within a valid logic level. we cannot determine the state the device comes up in, but that is not to say the device does not come up in a state.

Assume the crisscrossing connections are the same state at power up and S=0 and R=0, let's say 1. So each of the NOR gates will output a 0. This conflicts with the output of the other NOR output, so, for a brief moment(the propagation delay time), the inputs to the NOR gate will be 0 1, with an output of 1...it the delays are the same(if they are not, it will immediately settle), you have the same problem, and it may be erratic. Eventually, due to small imperfections in the devices themselves and external influences(capacitance, leakages, etc.) it will settle into a certain state and retain that state through positive feedback. That state, however, is indeterminate - we cannot predict what the state is.

EDIT: Some reading material:
http://www.allaboutcircuits.com/vol_4/chpt_10/2.html
http://electronics.stackexchange.com/questions/25629/how-does-a-latch-determine-its-initial-state
http://en.wikibooks.org/wiki/Digital_Circuits/Latches

 

We can not predict what state that is...as long as we carefully avoid designing our circuit in a way that will make it predictable.