# SR Flip Flop using D Flip Flop and other logic

Discussion in 'Homework Help' started by jegues, Oct 20, 2010.

1. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
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Question: Show how an SR flip - flop can be constructed using a D flip-flop and other logic gates.

Okay so the first thing I do is ask myself how an SR flip flop works. (Let's assume we're using a NOR SR FF)

Okay so if S = R = 0 then it will hold its state.(I.e. Q(t+1) = Q(t) )

If S = 0 and R = 1 then Q(t+1) = 0.

If S = 1 and R = 0 then Q(t+1) = 1.

If S = R = 1 then it's invalid.

Now I ask myself how does a D flip-flop works.

Well we know that a the output Q(t+1) is going to follow D only on the positive edge of the clock.

So the only time we care about is when our clock has a positive edge.

Now if our clock has a positive edge and D = 1 then Q(t+1) = 1.

Similarly, if our clock has a positive edge and D = 0 then Q(t+1) = 0.

If our clock doesn't have positive edge and D = 0/1 then Q(t+1) = Q(t).

Now back to the original question, I have to construct an SR flip-flop using D flip-flops and other logic gates. How do I work my way towards the solution?

I thought I had decent understanding of how SR and D flip-flops work but I don't know how to work my way towards a solution in a situation like this.

Thinking about the differences between and SR FF and D FF:

- An SR FF doesn't depend on any sort of clock, so somehow using D flip-flops and logic, I have to "eliminate" the clock in such a way that when values for S and R are applied, the clock will have a positive edge.

- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.

- An SR FF will hold its state when S = R = 0, while the D flip flop will hold its state while the clock is low (or on a negative edge). If I can guarentee that the when S = R = 0 that the clock is low(or on a negative edge) I should be able to manage the case S = R = 0.

I can't get any solid progress down on actually designing this thing. Am I attacking the problem in the wrong way? What should I be thinking about and what should I be asking myself?

Thanks again.

2. ### Kermit2 AAC Fanatic!

Feb 5, 2010
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- An SR FF (If we think about the SR NOR FF) is invalid for S = R = 1, so somehow I have to incorporate an "invalid state" using D flip-flops.

Rethink this portion first of all. Your instructions mentioned using 'other' logic gates as well to implement the S-R type of operation. How could you use AND and OR gates to set up a S=1 and R=1 exception?

3. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
45
Well if I ran S and R into a NAND gate, the output would be 1 expect for the case when S=R=1, then the output would be 0.

So the output of this NAND gate tell's us whether or not the SR input is valid. (i.e. it will output a 1 if the SR input is valid)

The covers 1 problematic area, right?

4. ### Kermit2 AAC Fanatic!

Feb 5, 2010
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Yes, and then you could approach the next problem area as well. The need for a clock pulse(think of it as an enable signal instead). Get your input for the clock circuit from your first D FF.

5. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
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I'm not sure how to go about managing this one, can you give me another hint?

6. ### Kermit2 AAC Fanatic!

Feb 5, 2010
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see next post

Last edited: Oct 20, 2010

Feb 5, 2010
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Sep 13, 2010
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9. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
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I'm still lost. These types of problems are extremely frustrating.

We've never done any examples of this type in class and my professor isn't able to help us. (He just gives us half ass answers)

I'm out of resources and I can't figure out what procedure to use to solve these problems. Can anyone suggest something?

10. ### Georacer Moderator

Nov 25, 2009
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This is another assignment in which I don't find any point in it. The D-FF is an evolution of the SR-FF. What is the point in using the D-FF to construct its predececor? Unspeakable words come to my mind.

First let's admit that you do want your circuit to operate with a clock. After all, you want to build an SR-FF, not an SR-latch. Note that wikipedia has a latch picture on the FF section. Look here, I think it's more illuminating. http://www.electronics-tutorials.ws/sequential/seq_1.html. It describes the NOR SR-FF, but basically you just invert the input, nothing too hard.

You want a logic circuit that will have as inputs S, R and Q (the output of the FF) and as an output the D (input of the FF). You want it to:

• Output D=0 when S=0 and R=1; (Q=both 1 and 0).
• D=1 when S=1 and R=0; (Q=both 1 and 0).
• D=Q when S=R=0.
• Since the inuts S=R=1 are invalid, I don't think anyone should ask for a specific behaviour in this case. So set D=X for S=R=1 and Q=both 1 and 0.
Make a Karnaugh table with 3 inputs S,R,Q and its ouput will be D. Seems pretty straightforward to me.
The clock will be drived the the D-FF clock.

11. ### jegues Thread Starter Well-Known Member

Sep 13, 2010
735
45
Thank you very much Georacer. What you stated worked perfectly.

Understanding what my inputs are and what my outputs are was a big help.

From here I could make myself a truth table as you mentioned. From the truth table I was able to generate minterms, and from there I could use a karnuagh map to simplify.

This is the "procedure" that I couldn't find anywhere. Atleast now for next I have a rough idea of what I should try and what I should be doing.

Again, thank you! (At this rate you've essentially replaced my professor)

Nov 25, 2009
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