spread spectrum implementation (using logic gates) for reducing EMC

Thread Starter

dileepchacko

Joined May 13, 2008
109
Hi All

My input signal is a varying duty cycle pulse (sign wave modulated) the frequency is fixed 26KHz. How I can change the frequency of the input signal +/-2KHz (24KHz to 28KHz) basically I would like to change the frequency of the input signal so that the emission is spread across the spectrum. I have implemented one circuit with d-flip flops an AND gates, but this approach is complex and more logic devices need to be used. Can anyone suggest simple logic circuit to implement this functions. Attached the circuit, using this circuit I can substract the single pulse from the input signal.

Thanks
Dileep
 

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DickCappels

Joined Aug 21, 2008
7,953
Here is a small 7 bit Barker code generator. It has the advantage of the being adjusted "by hand" without need for compiler. Baker codes spread things out a bit but it is more like chunky peanut butter than smooth peanut butter.
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1632839100092.png

Barker codes only get up lengths of 13 chips and so are more suitable for their correlation properties when decoding data modulated with the code than for their ability to spread. However, spreading is spreading so this might be enough.

1632839288610.png
This is a two-chip 8 bit maximal-length pseudorandom noise (pn) code generator. It should do a very nice job of spreading your signal around.

I have simulated both Barker code generators and the 8 bit maximal-length pn generators with AVR microntrollers. I have heard of this being done with a PIC and it seems that it would be easy to do with most other controllers.

Analog noise generators might be the best for your particular application since you just want to spread the code evenly and not worry about recovering anything.
1632839534584.png
You may need additional amplification to this analog noise depending upon how you want this noise to get into your clock circuit. It is a true random noise source, depending upon quantum events (tunneling) to generate an output. It is necessary to use the right power supply voltage because the circuits operation includes Zener-like charactaristics of the reverse-breakdown voltage of the emitter-base junction in Q1.
 

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Thread Starter

dileepchacko

Joined May 13, 2008
109
Hi, Thank you for the response and answerers. My understanding is that, you have tried to implement the pseudo random generator, but I already got the circuit, where I am facing challenge is that, how to modulate the random pulse into the input signal? As I mentioned in my question, the input signal is the 24KHz pulse signal with varying duty cycle, I would like to add or substract 2KHz into the input signal, but the duty cycle should not get effected.
 

Papabravo

Joined Feb 24, 2006
17,229
Do I understand the the output signal should preserve the duty cycle of the input and show up as either 22khz. or 26khz. If so that is not what spread spectrum is all about. I've also never seen a spread spectrum application that was done with logic gates alone. What leads you to believe that this is possible? I can see a digitally controlled VCO with discrete channels selected by a maximal length sequence generator. That seems to violate your original conditions.
 

DickCappels

Joined Aug 21, 2008
7,953
(Some text removed for clarity and brevity)

My input signal is a varying duty cycle pulse (sign wave modulated) the frequency is fixed 26KHz. How I can change the frequency of the input signal +/-2KHz (24KHz to 28KHz) basically I would like to change the frequency of the input signal so that the emission is spread across the spectrum. I have implemented one circuit with d-flip flops an AND gates, but this approach is complex and more logic devices need to be used. Can anyone suggest simple logic circuit to implement this functions. Attached the circuit, using this circuit I can substract the single pulse from the input signal.
A) Which circuit is represented in the attachment? Is it the pulse width modulation portion? There are many unlabeled inputs which makes guessing how the circuit works a very uncertain exercize.

B) Is the pulse width modulation signal itself available?

C) You mention spread spectrum, so can we assume that you want to cover many frequencies centered from 24 kHz through 28 kHz, or just the two?

You also wrote
"I would like to add or substract 2KHz into the input signal, but the duty cycle should not get effected."

D) This is a little more complicated part. Do you imagine the duty cycle will remain constant from pulse to pulse, or another way to do it might be to maintain the average duty cycle at the output as the same duty cycle as the input signal? (The answer to this may trigger additional questions)

From my guesses, this is not likely to be a simple logic circuit with few parts, but a better estimate might be generated from your responses to the questions above.
 

Thread Starter

dileepchacko

Joined May 13, 2008
109
Hi, I have only a simple PLD device (device cannot change in the board), so the device doesn't have more complex blocks like VCO etc..I have to implement the spread spectrum with the available logic gates.

I have attached the schematic for more clarity. Using the 4-bit LUT I will create 4-bit pattern in order to add or substract pulses from the input signal. A, B, C and D is the AND gate input, this input can be used to substract a pulse from the input. To modulate 2KHz frequency into the input signal (24KHz), I need to add or substract 3.78us pulse from the input signal. The 4 AND gates for substracting 3.78us pulse from the input signal. The 3.78us pulse will be divided by 16, because its 4-bit. I managed to substract the pulse from the input signal, but not able to add the pulse into the input signal. I have tried to use OR gates instead of AND gates to add the signal, but for some reason its not working.

Thanks
Dileep
 

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ronsimpson

Joined Oct 7, 2019
1,619
SSXO What are you using to generate the "clock". There are crystal oscillators that are Spread Spectrum and thus all logic generated from that clock source will be SS.
Cypress
SiTime
OR
Start with a high frequency oscillator like 64mhz and divide down to make the 26khz. The change the divide number every cycle. It is not necessary to randomly change the number. In switching power supplies they change the frequency by a triangle wave at 2khz. 64mhz to 64khz = divide by 1000. So start out with 1000, 1001, 1002 ...... Count from 968 to 1032 then back down to 968.
Programmable counter. About 1000 long.
Up/Down counter that counts from 968 to 1032.
1 bit counter for Up/Down.

RonS.
----edited to correct the counting----
 
Last edited:

Thread Starter

dileepchacko

Joined May 13, 2008
109
Thanks for your response and answer. The master clock is 12MHz, which is generated by the crystal oscillator. I can have the spread spectrum crystal oscillator, but I am not sure the CPLD will support the spread spectrum clock signal. The CPLD device I am using is LC4256V-75TN100 from Lattice Semiconductor. Its not clear from the CPLD datasheet that, the device can accept spread spectrum clock.

https://www.intel.com/content/www/us/en/support/programmable/articles/000080319.html

There are some information about the spread spectrum for FPGA from the above link, but not provided much details.

Thanks
Dileep
 

Sensacell

Joined Jun 19, 2012
2,917
SSXO What are you using to generate the "clock". There are crystal oscillators that are Spread Spectrum and thus all logic generated from that clock source will be SS.
Cypress
SiTime
OR
Start with a high frequency oscillator like 64mhz and divide down to make the 26khz. The change the divide number every cycle. It is not necessary to randomly change the number. In switching power supplies they change the frequency by a triangle wave at 2khz. 64mhz to 64khz = divide by 1000. So start out with 1000, 1001, 1002 ...... Count from 968 to 1032 then back down to 968.
Programmable counter. About 1000 long.
Up/Down counter that counts from 968 to 1032.
1 bit counter for Up/Down.

RonS.
----edited to correct the counting----
These spread spectrum oscillators are really neat! thanks for introducing this new idea!
 

ronsimpson

Joined Oct 7, 2019
1,619
but I am not sure the CPLD will support the spread spectrum clock signal.
I did not read the data sheet but most likely the CPLD will not care what the clock looks like from DC through 100mhz. If you clock has 5% variations in frequency the CPLD will not care.

Or you can use the logic in post #7.
12mhz/428= about 28khz, 12mhz/26=26khz, 12mhz/500=24khz. So change the master clock divide counter so it used numbers from 428 through 500. That will spread your noise out over 72 different frequencies.
 

Thread Starter

dileepchacko

Joined May 13, 2008
109
I did not read the data sheet but most likely the CPLD will not care what the clock looks like from DC through 100mhz. If you clock has 5% variations in frequency the CPLD will not care.

Or you can use the logic in post #7.
12mhz/428= about 28khz, 12mhz/26=26khz, 12mhz/500=24khz. So change the master clock divide counter so it used numbers from 428 through 500. That will spread your noise out over 72 different frequencies.
Hi , I Cannot use the the technique post #7 because I am not looking to generate the random clock signal, I needs to modulate the frequency into the input pulse, the input pulse is a varying duty cycle (sing wave modulated), need to change the frequency of the incoming pulse signal (24KHz), the counters will work on the fixed duty clock signals.

Thanks
Dileep
 

Thread Starter

dileepchacko

Joined May 13, 2008
109
Hi, I am not going to the spread spectrum crystal route, because its not clear from the CPLD datasheet that, the device can accept the spread spectrum crystal, can anyone suggest logic circuit to do the frequency modulation of input pulse.

Thanks
Dileep
 

DickCappels

Joined Aug 21, 2008
7,953
Would a simple shift register (parallel load) with a variable clock out be sufficient for your needs? You would load it once each PWM cycle, and you would probably have to pipeline a second register for continuous frequency modulated (yet preservation of duty cycle) output.
 

Thread Starter

dileepchacko

Joined May 13, 2008
109
Would a simple shift register (parallel load) with a variable clock out be sufficient for your needs? You would load it once each PWM cycle, and you would probably have to pipeline a second register for continuous frequency modulated (yet preservation of duty cycle) output.
Hi , thanks for your response , can you please sketch the circuit here for more clarity?

Thanks
Dileep
 

DickCappels

Joined Aug 21, 2008
7,953
1634310877019.png
It is a variable time "delay line".

A bit pattern is loaded into the Input Register.
At the right time, the Input Register is loaded into the Shift Register while simultaneously selecting a new shift clock.
This is repeated forever.

The timing can get hairy to maintain the duty cycle but the basic requirement is that entire cycles of the PWM signal are sent for before the clock clock frequency changes, this is what preserves the duty cycle as the frequency changes.

Possible drawback: May take a lot of shift register stages depending upon the resolution of the PWM signal.

That's as far as I've thought this through, figuring you know more about what you are doing than I do.
 

DickCappels

Joined Aug 21, 2008
7,953
Using a counter and magnitude comparators (compare the current count with registers holding the stop and start counts for the pulse, if a stop is even needed) to tell at which counts the pulse should change state might save a lot on shift register stages.
 
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